Timing Diagram 8085 Microprocessor

A timing diagram of a microprocessor depicts graphically the activities that are taking place at different instants of time (T states) inside the microprocessor.

As discussed previously, microprocessor fetches an instruction from the memory, decodes it, fetches the operands if required and then executes the instruction.

An execution of a instruction may take one to six machine cycles and a machine cycle may contain three or more T states. Before we study the timing diagram, the following terminologies should be clear.

Instruction cycle – It is the total time by the microprocessor to fetch, decode, fetch operands and execute the instruction.

Machine Cycle – It is time taken by the processor in completing the single task, for example fetching an OPCODE, Writing data to memory, or reading operands from the memory.

T States –  One clock period is referred to as one T states.  It is the basic unit used to calculate the time taken by the processor in execution of an instruction or a program.

Background:

Address Demultiplexing

To communicate the real world entities/peripheral, the address and data lines are first required to be demultiplexed. This is done by use of a latch. The latch is activated by an ALE signal. Input to the latch are the AD lines i.e. AD7 – AD0 as shown in figure below:

a high signal on th ale activates the latch. This latches the address A7 – A0 at the output of the latch. When the ALE signal is LOW, the AD7-AD0 lines can be used as data bus D7 – D0 so that they can be used for data transceiver.

Timing Diagram:

As said, the timing diagram  depicts graphically the activities that are taking place at different instants of time (T states) inside the microprocessor.

The figure below shows the timing diagram for an OPCODE fetch operation

At time T1 – the ALE signal goes high, this activates the 8-bit latch so that the address A7 – A0 is latched at the output of the latch

At time T2, the ALE signal goes LOW, and we see that the same lines now become the data bus D7 – D0

At this time the complete 16-bit address A15-A0 is available on the address bus.

Now the processor  puts a –ve going pulse on IO/M’ and RD’. This selects the memory unit for read operation. And the OPCODE from the address on the address bus is placed on the data bus.

Decoding the IO/M’ and the status lines

The IO/M’ along with the S0, S1 lines gives the status of the processor, what type of operation is being done inside the processor. These operations are:

IO/M’	S1	S0	Operation or the processor status
Z  “ High Impedance”	0	0	HLT
0	0	1	Memory Write
0	1	0	Memory Read
0	1	1	Opcode Fetch
1	0	0	X invalid
1	0	1	IO write
1	1	0	IO Read
1	1	1	Interrupt Acknowledge

 

So now we can draw the IO/M’ and S1 and S0 lines also in the timing diagram.

Example – Instruction Cycle for ADI AL, 56h

The timing diagram example for ADI 56 consist of two machine cycle

1. OPCODE fetch cycle
2. Memory read cycle.

The memory read cycle for the operand read is somewhat similar to OPCODE fetch operation, but requires only three T states.

The instruction ADI 56h is translated in the machine code as C6, 56 a two byte instruction stored in memory at two locations say:

• Opcode C6 at address 2001
• Operand 56 at address 2002

OPCODE fetch cycle (M1)

During machine cycle M1, the opcode C6 from address 2001 is read into the IR. This takes one machine cycle (M1) consisting of four T states T1 to T4.

Memory Read Operation

• Machine Cycle M2 represents the memory read operation of shown in the timing diagram. During T1 of M2 cycle, ALE signal goes HIGH to enable the latch and low byte address is latched at the output of the latch.
• The high byte of the address is already available on high order address bus. So during T1, full 16-bit address is on the address bus.
• During T2, the IO/M’ =0, and S1,S0 =10 indicating M2 is a memory read cycle.
• The data from address 2002 is put on the address bus and read into the processor.

Exercise:

Construct the timing diagram for the instruction LDA 4200h

Answer Hint:

This instruction requires four machine cycles consisting of 13 T states to execute. This is a 3 byte instruction stored as OPCODE followed by 16-bit address. Suppose the instruction is stored in memory starting from address 2000h as:

Opcode                      3A

Low order address   00

High byte address    42

The four machine cycles are:

• M1 consist of 4 T states to fetch the OPCODE from address 2000h
• M2 consist of 3 T states to fetch the low byte of address from location 2001
• M3 consist of reading high byte from address 2002
• M4 consist of 3 T states to read the data from address constituted in above 2 steps and put it into the accumulator

Memory Read Cycle:

The fetching the data from the memory is done during the memory read cycle.  The memory read cycle is similar to the op-code fetch cycle with the exception that :

1. the read cycle take 3-T states
2. the status and control signals

IO / M’	S1	S0	WR’	RD’
0	1	0	1	0

Memory Write Cycle.

This cycle is executed by the microprocessor when a data byte is to be written to memory. It take 3 T states to execute this cycle. It is executed when:

1. The control and status signals are :

IO / M’	S1	S0	WR’	RD’
0	0	1	0	1