8255 Programmable Peripheral Interface

8255 is a programmable peripheral interface IC which is used as an interface between the external device and the microprocessor for parallel communication. This IC is a 40-pi IC having three ports known as Port-A(PA), Port-B(PB) and Port-C(PC). these ports can operate in various modes. the complete details is given in the following PPTSs.

Features of the 8255:

• It provide three I/O ports
• All the three I/O ports are latched
• Port operation is configurable by programming 8255 i.e. writing a control word in CWR
• BSR- bit set-reset mode allows individual pins of port C to be controlled to be set or reset.

PIN diagram of 8255

8255 PPI is a 40-pin IC, it has three 8-bit ports named PA, PB and PC. It operates on a single +5V power supply.

PIN numbers	PIN name	PIN Functions
7, 26	GND, Vcc	Power supply pins
PIN 4 to 1 and PIN 40 to 37	PA(3-0) and PA(4-7)	Port A pins
pin 10 to 13 and pin 14 to pin 17	PC(7-4) and PC(0-3)	Port C pins
Pin 18 to pin 25	PB (0-7)	Port B pins
Pin 5,6,8,9, 35,36	RD’, CS’, A1, A0, Reset, WR’	Control signals- read,chip select and port/cw address bits, reset and write pins
Pin 34 to pin 27	D(0-7)	Data pints from/to microprocessor Block Diagram of 8255

Block Diagram of 8255

8255 is a general purpose programmable peripheral interface. Different com

ponents of the 8255 are explained below:

Data bus buffers:

This unit is used to communicate with the data bus of the microprocessor. It is also connected to the internal bus of the 8255 so that the data can be received or transmitted from or to any of the three ports.

Read/write Control unit :

This unit contains all the control signal and the control word. The control signals are: read (RD’), write(WR’), port address(A1,A0), RESET and chip select (CS’). CS’ signal is generate by logic gates or decoder using the address bit specified for the operation of the 8255.

GpA and GpB control units:

These units are used to carry the contro signals for the three ports PA, PB, PC

 

Ports -PA, PB, PC:

8255 has three ports which have their inputs and outputs latched. Threse ports can be controlled for different modes of operations. Control word can be written in the control word register for setting the mode of operations.

Port Selection:

Port selection address depend on whether the data bus of the 8255 is to be connected to lower or upper data bus of the 8086 microprocessor. For transmission on the low order data bus (D0-D7) the port address to be generated must be even address. But if the data is to be communicated over high order data bus (D8-15) the port address to be generated must be odd address. However for 8085 microprocessor the port address can be contiguous addresses.

Chip Select and Port addresses for interfacing with 8086

Assuming the data buffer of 8255 connected to low-order data bus of 8086. three ports and control word addresses must be the even address. For generating these even addresses, address line A0 from 8086 must be used in chip select CS’ generation.

Assume 8-bit port addresses, A1,A0 pins of 8255 must be connected to A2,A1 address lines of the 8-address lines A7-A0 of 8086. There could be different combinations of addresses, one such address combinations may be:

A7	A6	A5	A4	A3	A2	A1	A0	Port Address	PORT selected
0	1	0	0	0	0	0	0	40h	PA
0	1	0	0	0	0	1	0	42h	PB
0	1	0	0	0	1	0	0	44h	PC
0	1	0	0	0	1	1	0	46h	CW

Operating Modes of 8255

8255 has three ports which can operate on different modes selected by writing a control word in its control register (CWR). Broadly the modes are classified as :

• BSR – bit set reset mode : This mode is used to set or reset the port ‘C’ pins.
• I/O  Mode – There are three i/o  modes. These are Mode-0, Mode-1, Mode-2
• Mode 0 Basic Functional Definitions:
  • (i) Two 8-bit ports and two 4-bit ports, Any Port can be input or output
  • (ii)Outputs are latched
  • (iii) Input are not latched
• Mode1BasicFunctionDefinitions:
  • (i) Group A and Group B i/o with and Port C 4-bit control/data port for PA and PB
  • (ii) Both inputs and outputs are latched.
  • (iii) The 4-bit ports of PC is used for control and status of the 8-bit port.
• Mode 2 Basic Functional Definitions :
  • (i) Gp-A used as 8-bit, bi-directional bus with port-C as 5-bit control bits
  • (ii)The 5-bit control port (Port C) is for the 8-bit, bi-directional bus port (Port A)
  • (iii) Both inputs and outputs are latched

Control Word format

D7	D6	D5	D4	D3	D2	D1	D0
Mode Set	GpA mode Select		PA I/O	Port-C upper PCL I/O	GpB mode control	PB I/O	Port-C lower PCL I/O
0- BSR 1-I/O	0 0 Mode-0 0 1 mode-1 1 X Mode-2		0 – o/p 1 – i/p	0 – o/p 1 – i/p	0 – Mode-0 1- Mode-1	0 – o/p 1 – i/p	0 – o/p 1 – i/p

Bit set-Reset (BSR) Mode

Bit Set/Reset (BSR) Mode of Operation : BSR mode is used for Port-C to control read/write operation on individual pins of port C. The control word of the BSR mode is shown in figure

I/O Mode of operation

The IO mode is used for reading and writing from or to IO device. The read write operations to/from IO devices can be performed in different modes. The control word setting for the IO mode is shown

examples:

 

8255 Part-1

8255 Part-2

8255 Part-1 8255 Part-2 8255 PPI Part-3