Interrupt is one of the most common methods for an external device to communicate with the processor. In small systems, for example, we might read ASCII characters on interrupt basis, count interrupt from a timer to produce real time clock or seconds, minutes and hours; detect several emergency conditions on interrupt basis.

Figure-1: A basic interrupt system

Figure-1 below shows a general concept of the interrupt in our day-to-day activity. Suppose we are enjoying listening to music, if now phone bell rings, we stop or pauses our music and attends the phone, after conversation is completed, we again restart the paused audio and continue to listen the music.

We would not our audio every minute to check if phone bell is ringing, which would be an inefficient and slow method.

Our computing device behaves a similar way. There are two ways a CPU can interact with the external devices that are connected to it. One method is polling and the second interrupt.

Polling: In this method the processor will be checking at regular intervals if any of the external device needs service. With this method the processor will be wasting most of its time checking the device instead of doing some useful tasks.

Interrupt: The processor can continue it productive task. Whenever any device wishes to communicate, it will do so by requesting the attention of the CPU. The request may go unnoticed if the processor is executing some higher priority tasks or may give its attention (processing time) and requested service provided to the device. When the processor listens to the interrupt it suspends its current job and takes care of interrupting device. Once the required service is given to the device, the processor goes back to handle the previously executing task.

Interrupt Service Routine:  Interrupt service routing are special programs in the computer memory. Each device attached to the processor will have a specific service routing in the computer memory. The ISR contain enough logic to service or to take care of the interrupting device. Whenever any device interrupts the processor, the CPU stops the execution of the current program, save the contents (pushes on stack) of registers(PC, flags, accumulator) and jumps to the service routine of the interrupting device. At the end of the execution of service routine, the saved registers are (POPed out) restored, and the earlier program execution continue thereon.

Interrupt Priority:If more than one external device request for the CPU attention, the CPU attention is seeked by following the interrupt priority methods. The interrupt priorities determine which device receives the processor’s attention when more than one device is simultaneously requesting an interrupt via the IRQ line. The  common methods are:

  1. Fixed Priority
  2. Daisy Chaining
  3. Fixed Priority: in this system each interrupting device connected to the processor is given an interrupt number and each interrupt number is given a fixed priority number. Normally a IRQ 0 is given to the highest priority and the next lower priority is given to the INT 1, INT 2 and so on.

This means that if IRQ 0 is executing at any point then other interrupts cannot gain control of the processor or cannot interrupt. Whereas if interrupt 2 is being serviced and INT 0 or INT 1 both having higher priority can interrupt INT 2 process. If we donot want the IRS for interrupt 2 to be interrupted, then INT 2 interrupt service program  should have an instruction Disable all interrupts, this will disallow any new interrupt interrupting the CPU until the ISR has been executed completely.

On many computers a highest priority interrupt is activated by a power failure.

Power Fail interrupts:

Most CPU operates on 5V supply generated from normal AC supply line. Power failure may be detected when AC power falls below 80% of the normal supply.

It may take few thousandths of a seconds before power drops so loaw that +5V cannot be maintained by computer power supply. In these few milliseconds, a hundred or more instructions can be executed by the power fail interrupt routine to prepare the system for power failure in an orderly fashion; so that when the power comes up again, a power fail interrupted program can restart without any loss of data.

  1. Daisy Chaining:

Daisy chaining is a simple hardware means of attaining priority scheme. It consist of associating a logic circuit with each interface  and passing the interrupt acknowledge signal through these circuits as shown in figure. In this method each device is connected to a single IRQ line, and a low interrupt  INTA’ from the processor is given to the first device on the chain because this device has the highest priority.  A simplified diagram of this scheme is shown in figure-2 below.

Figure-2: A simple Daisy chain

A more detailed diagram is shown with the daisy chain. Here device requesting the service raises a high INTR signal, which is passed to processor.

Figure-3: A Detailed logic for Daisy Chain

The processor in response generates an low INTA’ acknowledgement and it first goes to device-1 interface. If device -1 had not requested the service its INTR line is low(‘0’), so INTA’ is passed without modification by the daisy chain to the next device interface. If device 2 had requested for the interrupt, this INTA’ get recognized by its daisy chain and in turn the interface gives the device type and code to the processor through data bus. The processor, by reading this number, will know which device need its attention and thus starts the interrupt service routine for that device and complete the interrupt sequence eventually dropping its request as it is serviced.

This system is suitable when the number of device in the daisy chain are small as the last device in the chain will get the little attention of the CPU, also the system becomes very slow and inefficient for large number of devices.

Interrupt Overview

System employing advanced interrupt system mechanism the following interrpt procedure to handle the interrupt. For an 8086 system for example, If the 8086 interrupt flag is set and INTR input receives a high signal, 8086 will:

  1. Push the Flag on the stack
  2. Clear the IF and TF
  3. Push the return address on the stack
  4. Put the data bus in the input mode
  5. Send out two interrupt acknowledge pulses on the INTA’ pin. The INTA’ pulse tell some external hardware device such as an 8259A to send the desired interrupt type to the 8086
  6. When the 8086 receives the interrupt type from the external device, it will multiply that interrupt type by 4 to produce an address in the interrupt pointer table
  7. From the address and the three following addresses the 8086 gets the IP and CS values for the start of the interrupt service procedure. Once these values are loaded  into the CS and IP, the 8086 then execute the interrupt service procedure.

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