8259 Priority Interrupt Controller

8259 Programmable Interrupt Controller

The Intel 8259A programmable Interrupt Controller (PIC) is one of the most common interrupt controller used in IBM PCs. It can handle eight vectored priority interrupts for the CPU. It is a 28 pin DIP package and requires a single +5V DC supply for its operation. It is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of system requirements. The pin diagram of 8259A is shown in figure-1 below.

Figure-1: 8259 PIN Diagram

PIN Number Pin Name Description
1 CS’ Chip Select Input
2 WR’ Write control signal
3 RD’ Read control signal
4-11 D7-D0 Data Bus
12-13, 15 CAS0, CAS1 Cascade control
14 GND Ground
16 SP’/EN’
17 INT Interrupt output for processor
18-25 IRQ0 – IRQ7 Interrupt request inputs
26 INTA Interrupt Acknowledge input
27 A0 Address input
28 VCC +5V supply

 

8259 interrupt Overview

If the 8086 interrupt flag is set and INTR input receives a high signal, 8086 will:

  1. Push the Flag on the stack
  2. Clear the IF and TF
  3. Push the return address on the stack
  4. Put the data bus in the input mode
  5. Send out two interrupt acknowledge pulses on the INTA’ pin. The INTA’ pulse tell some external hardware device such as an 8259A to send the desired interrupt type to the 8086
  6. When the 8086 receives the interrupt type from the external device, it will multiply that interrupt type by 4 to produce an address in the interrupt pointer table
  7. From the address and the three following addresses the 8086 gets the IP and CS values for the start of the interrupt service procedure. Once these values are loaded  into the CS and IP, the 8086 then execute the interrupt service procedure.

Functional Description of 8259A

8259A is used to manage the interrupt requirement of the system. It has 8 interrupt input lines through which it accepts interrupt requests from external devices and determines the priority of the incoming request and issues a interrupt to the CPU. The interrupt inputs are extendable up to 64 levels.  And subsequently inputs information related to ISR so that the processor can initialize the program counter with the ISR address of the interrupting device. It is programmed as an i/o device  and provides number of interrupt modes to the programmer so that the manner in which the requests are processed by 8259 can be configured to match the system requirement. Figure below shows the functional diagram of 8259A.

Figure-2: Block diagram of 8259

The block diagram in figure-2 shows the following sub components of 8259A

  1. Data Bus Buffer
  2. Interrupt Request Register
  3. In-Service register
  4. Priority Resolver
  5. Interrupt mask Register
  6. Read / Write Logic
  7. Cascade Buffer/Comparator

Data Bus Buffer: It is a bidirectional 8-bit register. CPU transfers the Control and status information through this buffer to 8259A; similarly 8259 transfers the vector address information to data bus through this buffer. On the CPU side it is connected to the 8-bit data bus and on the other side it is connected internally to the internal data bus.

Interrupt Request register and In-Service register:

The interrupt requests from the external devices IRQ lines are handled by these two registers in cascade. IRR is used to latch the incoming request and, in conjunction with priority resolver, allows unmasked requests with sufficient priority to put a ‘1’ on the INT pin.  ISR is used to store all the interrupts that are being serviced by the CPU.

Priority resolver:

The logic block determines the priority of the services being in-request in the Interrupt Request Register. The highest priority is selected and sent to the ISR during INTA pulse.

Interrupt Mask register:

The IMR stores the masking information for the interrupt lines. The IMR operates on the IRR. Masking of a higher priority interrupt will not disable or mask the interrupt request lines of lower priority.

Interrupt (INT) and Interrupt Acknowledgement (INTA)  :

INT output from 8259A goes to CPU interrupt input. This line is used to inform the CPU about the interrupting device that is interrupting the processor. INTA pulse will make the 8259A to release vectored address information of the interrupt service routine (ISR) onto the data bus.

Read/Write Control Logic:

The function of the R/W logic is to accept the commands from the CPU. It consist of an initialization Command Word (ICW) registers and Operation Command register (OCW) registers which store various control formats. It also allows the status of 8259 to be transferred to data bus. It has the following control signals:

Chip Select (CS’): It is a low active signal is used to select the chip. No operation is possible until Chip is selected through this input.

Write (WR’) and Read (RD’):

These are two low active signal used for read and write operations. WR is used to write control words (ICWs and OCWs) to 8259A and read (RD’) is used to read the status information  of IRR, ISR, IMR or the interrupt level to the data bus.

Address input (A0):

The Address input A0 from the processor can be directly connected to A0 pin of 8259A and is used with RD’ and WR’ to write commands and to select various status registers for read operation.

Cascade Buffer / Comparator:

For one of the two purposes; either as an input to determine whether 8259A is to be master (SP’/EN’ = 1) or as slave (SP’/EN’ = 0), or as an output to disable the data bus transceiver when data are being transferred from the 8259A to the CPU.

This block is of importance when more than eight interrupts are to be used. This allows multiple 8259A to be cascaded for this purpose. It compares the IDs of all 8259As. CAS0-to-CAS2 are outputs from 8259A when used as master and are inputs when used as slave. As a master, 8259A sends the IDs of the interrupting slave device onto the CAS0-CAS2 lines. The selected slave device will send its pre-programmed subroutine address onto the data bus during the next one or two consecutive INTA pulses.

Interrupt Sequence of 8259A:

The main feature of 8259A is its programmability and the interrupt routine addressing capability. The addressing capability allows direct or indirect jumping to specific ISR based on the interrupt number and the interrupting device.  The normal sequence of events during an interrupt depends on the type of the CPU used and are given below:

  1. After a bit in the IRR is set to ‘1’ it is compared with the corresponding mask bit in IMR. If the mask bit is 0, the request is passed to the priority resolver, but if it is 1, the request is blocked.
  2. When an interrupt is input to the priority resolver its priority is examined and. If according to the current state of the priority resolver the interrupt is to be sent to the CPU, the INT line is activated.
  3. Assuming that the IF flag in the CPU was set to 1, the CPU will enter its interrupt sequence at the completion of the current instruction and return two negative pulses over the INTA’ line
  4. Upon receiving the 1st INTA’ pulse, the IRR latches are disabled, so that the IRR will ignore further signals on the IR7-IR0 lines. This state is maintained until the end of the 2nd INTA’ pulse.
  5. Also the 1st INTA’ pulse will cause the appropriate ISR bits to be set and the corresponding IRR bit to be cleared.
  6. The second INTA’ pulse cause the current content of ICW2 to be placed on D7-D0, and the CPU uses this byte as the interrupt type.
  7. Now if the automatic end of interrupt (AEOI) bit ICW4 is 1, at the end of the second INTA’ pulse the ISR bit that was set by 1st INTA’ pulse is cleared; otherwise, the ISR bit is not cleared until the proper end of interrupt (EOI)command is sent to OCW2

Command Words

8259A has two types of command words, initialization and operational control word.

  1. Initialization command word:
    1. ICW1 for chip (8259A) control
    2. ICW2 for type
    3. ICW3 for status control
    4. ICW4 for mode control
  2. Operational Command Word: OCW1, OCW2, OCW3

The initialization control words are normally set by the initialization routine when the computer system is first brought up and remains constant throughout its operation. The operational command words are used to dynamically control the processing of the interrupt.

Various Command Words of 8259

The formats of various command words are given below:

Initialization command word: ICW1 (chip control):

7 6 5 4 3 2 1 0
Not Used by 8086/8088 system

But used in 8080/8085 system

Always ‘1’ LITM ADI SNGL IC4
It directs received by to ICW1

(it should be OCW1)

Whether edge trigger(LITM=0) or level trigger(LITM=1)  mode is used Used only in 8085 Single(SNGL=1) or cascade(SNGLE=0) IC4=1, if ICW4 is to be output during initialization sequence

 

ICW2 (Type)

7 6 5 4 3 2 1 0
Filled from bit 7-3 of the 2nd byte output by the CPU during the initialization of 8259A Bit 2-0 are set according to the level of the interrupt request
IR6 would cause bit 2-0 to 110 and so on

 

 

ICW3,

ICW3 is significant only in systems including more than one 8259A and is output only if SNGL=0

 

 

ICW4

ICW4 is output to only if IC4 (ICW1) is set to 1; otherwise, the content of ICW4 is cleared. The bits in ICW4 are as follows

7 6 5 4 3 2 1 0
Always set to 0 SFNM BUF M/S (1/0) AEOI uPM
=1, if special fully nested mode is used in more than one 8259A =1, indicate SP’/EN’ is to be used as an o/p to disable system 8286 txr while CPU i/p data from 8259A. SP’/EN’ should be =1 Ignored if BUF=0; otherwise 1 for master, 0 for slave If 1, the ISR bit that caused the interrupt is cleared at the end of 2nd INTA’ pulse =1 to indicate 8259A is in 8086 based system. 0 indicate that 8259A is in 8085 based system

 

Operational Command Word:

OCW1 is used for masking the interrupt request; when the mask bit corresponding to  an interrupt request is 1, then the request is blocked. OCW2 and OCW3 are used for controlling the mode of the 8259A and receiving EOI commands. A byte is transferred to OCW1 by using the odd address (A0=1) associated with 8259A and bytes are output to OCW2 and OCW3 by using even address (A0=0). OCW2 is distinguished from OCW3 by the contents of bit-3 of data byte. If bit-3 is 0, the byte is put in OCW2, and if it is 1, the byte is put in OCW3. Both OCW2 and OCW3 are distinguished from ICW1, which also uses even address, by the content f bit-4 of data byte. If content of bit-4 of data byte is 0, then byte is put in OCW2 or OCW3 according to bit-3. There is no ambiguity in ICW2, ICW3, ICW4 and OCW1 all using the odd address because initialization word must always follow ICW1 as dictated by initialization sequence.

OCW1:

7 6 5 4 3 2 1 0

 

 

OCW2

7 6 5 4 3 2 1 0
R SL EOI 0 0 L2 L1 L0
Used for controlling the IR levels Used for giving EOI command SED FOR DESIGNING ir LEVEL

 

R             SL

0              0              Nonspecific, normal priority mode

0              1              Specifically clears the ISR bit indicated by L2-L0

1              0              Rotate priority so that a device after being serviced has the lowest priority

1              1              Rotate priority until position specified by L2-L0 is lowest

 

OCW3

7 6 5 4 3 2 1 0
0 ESMM SMM 0 1 P RR RIS

 

8086 Example:

A typical program sequence for setting the content of ICWs, which assume the even address of the 8259A is 0080h, is given below:

MOV     AL, 13h ; ICW1 indicating request to be edge trigger, use one 8259A, ICW4 to be output

OUT       80h, AL

MOV     AL, 18h ;  cause 5 MSBs of interrupt type to be set to 00011

OUT       81h

MOV     AL, 0Dh; informs the 8259A that SFNM is not to be used, SP’/EN’ used to disable TXR, and

; 8259A is master, EOI used to clear ISR bit, and 8259A is part of 8086 system

OUT       81h, AL

 

First two instructions causes the requests to be edge triggered, denote that only one 8259A is used

 

Updated: April 5, 2020 — 2:07 pm

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