Binary Counter Design

Sequential-Synchronous Counter Design

The different steps for the design of the synchronous sequential counter circuits are:

i)          State diagram

ii)         state table and  excitation table

iii)        Simplification using K-Map

iv)         Logic Design

Number of Flip-Flops required for implementing a counter:

  1. For N-bit counter, N flip-flops would be required
  2. For counter counting upto  N states, the number of flip-flops required would be :                                              No._of_FFs = Log2 N  = Log2 2n

Let us now start with the design problems.

 

Example-1: Design a 4-bit synchronous up counter using T flip-flops

Step-2: The Excitation Table

State

Excitation

PS NS T1 T2 T3 T4
0000 0001 0 0 0 1
0001 0010 0 0 1 1
0010 0011 0 0 0 1
0011 0100 0 1 1 1
0100 0101 0 0 0 1
0101 0110 0 0 1 1
0110 0111 0 0 0 1
0111 1000 1 1 1 1
1000 1001 0 0 0 1
1001 1010 0 0 1 1
1010 1011 0 0 0 1
1011 1100 0 1 1 1
1100 1101 0 0 0 1
1101 1110 0 0 1 1
1110 1111 0 0 0 1
1111 0000 1 1 1 1

 

Step-3: Logic Equations for Inputs

T1        =          Q1’Q2Q3Q4  +  Q1Q2Q3Q4

T2        =          Q1’Q2’Q3Q4 + Q1’Q2Q3Q4 + Q1Q2Q3Q4 + Q1Q2’Q3Q4
T3        =          Q1’Q2’Q3’Q4 +Q1’Q2’Q3Q4 + Q1’Q2 Q3’Q4 + Q1’Q2Q3Q4 + Q1Q2Q3’Q4 + Q1Q2Q3Q4                                    + Q1Q2’Q3’Q4 +Q1Q2’Q3Q4
T4        =          1 (All min-terms have high value)

Step-4: Simplification of above Boolean Equations

Figure-2: Solution of Boolean Equations

Step-4: The Logic Diagram of a 4-bit Binary Counter

 

Figure-3: Logic Diagram of a 4-bit Binary Counter

 

Example:Design a 3-bit Binary up/Down Counter using ‘T’ Flip-Flops

A 3-bit counter would require 3 flip-flops. A switch input ‘x’ is required to set the counter in incrementing or in decrementing mode. When x=0, the counter counts UP,  if x=’1’, the counter counts DOWN.

Step-1: State diagram

 

Figure-1: State Diagram of 3-bit Up/Down Synchronous Counter

Step-2: Construct the truth table from the state diagram

State Excitation
Control Input (x) PS

Q1Q2Q3

NS

Q1Q2Q3

T1 T2 T3
0 000 001 0 0 1
0 001 010 0 1 1
0 010 011 0 0 1
0 011 100 1 1 1
0 100 101 0 0 1
0 101 110 0 1 1
0 110 111 0 0 1
0 111 000 1 1 1
1 000 111 1 1 1
1 001 000 0 0 1
1 010 001 0 1 1
1 011 010 0 0 1
1 100 011 1 1 1
1 101 100 0 0 1
1 110 101 0 1 1
1 111 110 0 0 1

 

Step-3: Write the SOP equations

T1   =     x’Q1’Q2Q3 + x’Q1Q2Q3 + xQ1’Q2’Q3’ + xQ1Q2’Q3

T2   =     x’Q1’Q2’Q+ x’Q1’Q2Q+ x’Q1Q2’Q+ x’Q1Q2Q+ x Q1’Q2’Q3

+ xQ1’Q2Q3’ +  xQ1Q2’Q3’ + xQ1Q2Q3

T3  =    1

Step-4: Simplify the SOP Equations

Figure-2: K-Map solution for T1, T2, T3 inputs

Step-5: Draw the logic Diagram

Figure-3: A 3-bit Binary Up-Down Counter Circuit

Figure -Logic Circuit

Exercise:

  1. Design a two bit binary counter such that when a push switch is closed the count decrements else the count remain unchanged.

 

Updated: September 12, 2019 — 6:02 pm

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