8051 Memory Organisation and SFR

Memory Organization of 8051 Microcontroller

8051 micro-controller is based on the Harvard architecture, which supports separate program memory and separate data memory. The following paragraph explains the memory supported by 8051.

Program Memory

8051 supports 4 KByte internal and 60 KByte external i.e. a total of 64 KByte of program memory.

Selection of Program memory

8051 has an external access (EA) for selection of internal or external program memory. When EA=1; internal 4 KByte ROM is first fetched, control automatically transfers to external ROM once internal program memory limit is exceeded.

When EA=0; Only the external program memory is accessible. So, the internal program memory is bypassed. Figure 6.1 shows the program memory of 8051

Figure 6.1 Program memory arrangement

 

Internal Data Memory

8051 has 256 byte internal data memory of this the lower 128 byte supports four register, 16 byte bit/byte addressable memory and rest 80 bytes of scratch pad area for user data. Out of the upper 128 byte memory only 21 locations are used as special function registers. The internal data memory arrangement is shown in figure 6.2.

Figure 6.2 Internal Data Memory

 

Register Bank Selection

Figure 6.3 shows the register of four banks and their addresses.

Figure 6.3 Register Banks and their addresses

When the 8051 is power, by default, register bank-0 is selected, therefore by default R7-R0 refers to bank-0. example below shows the program usage:

Case-1

Calling registers by their names

Case-2

Calling Registers by their address

MOV R1, #058h

MOV R2, #55h

MOV R7, #99h

MOV 00h, #78h  ; same as MOV R0, #78

MOV 07, #65h

MOV 05, #24h

If the programmer  wish to use register of any other bank, he has to explicitly select by setting or clearing PSW.4, PSW.3 bits in flag register.

Case-1 Case-2
SETB PSW.4     ; RS1=’1′

CLR PSW.3       ; RS0=’0′

MOV R5, #97h    ; load R5 of bank-2

 

SETB PSW.3

CLR PSW.4       ; selects bank-1

MOV R3, #92h

MOV A, R3

SETB PSW.4

CLR PSW.3       ; selects bank-2

MOV R3, A

Special Function Registers (SFR)

SFRs in 8051/8052 controllers are accessed as if they were normal Internal RAM locations. The only difference is that Internal RAM is from address 00h through 7Fh whereas SFR registers exist in the address range of 80h through FFh.  Of the upper 128 byte from 80h to FFh, only 21 locations in case of 8051 are usable as SFR, read accesses to other than these addresses will in general return random data, and write accesses will have an indeterminate effect. Table 6.1 shows all the SFR and their memory location

TABLE 6.1: Special Function Register SFR in 8051; * are additional SFR in 8052
0F8h 0FFh
0F0h B 0F7h
0E8H 0EFh
0E0h ACC 0E7h
0D8H 0DFh
0D0h PSW 0D7h
0C8H T2CON* T2MOD* RCAP2L* TL2* TH2* 0CFh
0C0h 0C7h
0B8H IP 0BFh
0B0h P3 0B7h
0A8H IE 0AFh
0A0h P2 0A7h
98H SCON SBUF 9Fh
90h P1 97h
88H TCON TMOD TL0 TL1 TH0 TH1 8Fh
80h P0 SP DPL DPH PCON 87h
0 1 2 3 4 5 6 7

All these special function registers may be categorised as per their functionality such as given in table 6.2

TABLE 6.2: Categorization of SFR

Sl Category Special Function Register (SFR)
1 I/O Port s P0, P1, P2, P3
2 Math or CPU Registers A, B
3 Pointer Register DPL, DPH, SP
4 Peripheral Control Registers: PCON, SCON, TCON, TMOD, IE and IP
5 Peripheral Data Registers TL0, TH0, TL1, TH1 and SBUF

 

Data Pointer SFR (DPTR)

DPTR is made of two 8-bit register (DPH and DPL) as shown in figure 6.4. DPTR itself  doesn’t have a physical Memory Address but the DPL (Lower Byte of DPTR) and DPH (Higher Byte of DPTR) have separate addresses in the SFR Memory Space. DPL = 82H and DPH = 83H.

DPTR Register is used by the programmer addressing external memory (Program – ROM or Data – RAM)

Figure 6.4 dptr

How to Use DPTR in 8051 programming

MOV DPH, #0A1h     ; load high byte address in DPH

MOV DPL, # 05h       ; Load low byte address in DPH

MOVX A, @DPTR     ; moves a data byte from external memory in accumulator

MOVC A, @+DPTR

Stack Pointer (SP) SFR

Stack pointer register is used to point to the stack area of the RAM. By default, the SP contains the value 07h which means the next location i.e. 08h is the first stack location which is also the location of R0 in ragister bank-1. Stack supports two operations PUSH and POP. A PUSH operation save a register value on stack whereas a POP operation is used to read a value from stack to a register. locations 08 to 1F is also be used for stack operation.

Locations from 20 to 2Fh must not be used for stack as these are reserved for bit address memory.

However, if the programmer need more stack area then he can do so by pointing to scratch pad area of the memory by using the instruction :

  • MOV SP, #xxh

How to use stack memory

Notice carefully that to push, we need to give register address as argument to PUSH instruction.

As the PUS operation increments the SP and POP operation decrements the SP, so on decrement SP should not go to location 6,5,… Also if the programmer need bank-1 and bank-2 registers, he should reallocate the stack are of memory to upper RAM locations  60h to 7Fh

Example: Referring to lines of code given below, show the stack pointer and the memory content after each PUSH operation

MOV R1, #15h

MOV R2, #0F1h

MOV R3, #52h

PUSH   1

PUSH   2

PUSH   3

Solution

Figure 6.5 stack PUSH

Program Status Word (PSW) Address 0D0h

It is an 8-bit register, it indicates the status of the accumulator after each operation. PSW is also used to select the register bank in 8051 controller. The format of the program status word (PSW) is shown in figure 6.6

Figure 6.6 PSW

Power Control (PCON) SFR (87h)

Power control register is located at address 87h. The two functions provided by PCON register is:

  • Idle Mode
  • Power Down Mode
  • Buad rate for Serial port

Idle Mode:

In Idle mode the 8051 stops the clock signal to ALU, but provides the clock to other peripheral like timers etc.

Power Down Mode:

In power down mode, the oscillator will be stopped and power reduced to 2V

Figure 6.7 PCON

SCON Register

SCON is a serial control register in 8051. It is located at address 98h. It is used to  control the Operation Modes of the Serial Port, Baud Rate of the Serial Port and Send or Receive Data using Serial Port. The format of the SCON register is shown in figure 6.8

Figure 6.8 SCON Register

 

BIT Name Function
SCON.7 SM0 Serial Mode Transfer bit
SCON.6 SM1 Serial Mode Transfer bit
SCON.5 SM2 Used in multi-processor mode. For single processor make it ‘0’
SCON.4 REN Set by software to enable / disable reception
SCON.3 TB8 Normally not used
SCON.2 RB8 Normally not used.
SCON.1 T1 Transmit Interrupt Flag. Set by hardware at the beginning of the stop bit in mode-1. Must be cleared by software
SCON.0 R1 Receive interrupt flag. Set by hardware halfway through the stop bit time in mode-1. Must be cleared by software

Serial Mode Transfer setting

SM0 SM1 Mode Description Baud Rate
0 0 0 8-Bit Synchronous Shift Register Mode Fixed Baud Rate

( Frequency of oscillator / 12)

0 1 1 8-bit Standard UART

mode

Variable Baud Rate (Can be set by Timer 1)
1 0 2 9-bit Multiprocessor Comm. mode Fixed Baud Rate

( Frequency of oscillator / 32 or Frequency of oscillator / 64

1 1 3 9-bit Multiprocessor Comm. mode Variable Baud Rate (Can be set by Timer 1)

Timer Control (TCON) Register

Timer control register is accessible at upper RAM area at address 88h. This register is used to control the start and stop of the timers T1 and T0.

 

Figure 6.9 TCON

TF1 : Timer-1 overflow flag, Set when time-1 overflows and rolls back

TR1: Timer-1 start/stop bit by program. Set to start the timer, cleared to stop the timer

TF0: Timer-0 overflow flag, Set when time-1 overflows and rolls back

TR0: Timer-0 start/stop bit by program. Set to start the timer, cleared to stop the timer

IE1: This bit is set by the processor if there is an interrupt at INT1, cleared when there is a jump to ISR of INT1

IT1: set this bit for interrupt generated by a low level signal at INT1; clear this bit for an interrupt generated by falling edge signal at INT1

IE0:  This bit is set by the processor if there is an interrupt at INT1, cleared when there is a jump to ISR of INT1

IT0:  set this bit for interrupt generated by a low level signal at INT1; clear this bit for an interrupt generated by falling edge signal at INT1

TMOD Register Address 88h

TMOD register is used to select the timer/counter and mode of operation. It is at address 89h in upper memory. The format of the TMOD register is shown in figure 6.10. Lower nibble sets mode for timer-0, and the upper four bit are used to set the mode for timer-1

Figure 6.10

GATE = 1           Timer is operated only if INT1 is SET

Gate = ‘0’           Timer is operates irrespective of INT1 pin.

C/T’  Operates as timer if ‘0’ else counter to count external events

M1  M0       Mode

0      0           0                13 bit counter 8 bit in TH count and 5 bit in TL pre scalar

0      1             1                16 bit counter

1      0            2                 8 bit counter with auto reload

1      1            3                 Split mode

 

Interrupt Enable SFR

IE register is used to enable / disable the interrupt in 8051. The register is accessed at memory location A8h. It is a bit addressable registers. The bits can be accessed by their name i.e. SETB  IE.7 or by their bit addresses as SETB 0AFh. Figure 6.11 shows the bit address and their functional names.

Figure 6.11 IE register

Updated: June 10, 2019 — 3:11 pm

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