A bus cycle or machine cycle defines the sequence of events when the MPU communicates with an external device such as memory or I/O, which starts with an address being output on the system bus followed by a read or write data transfer.
An instruction cycle consists of :
A program consists of number of instructions which are stored in memory. These instructions are to be fetched from the memory and decoded to generate the necessary timing and control signals, an instruction may also contain data or a reference to a data that are also required to be read and then the CPU carries out the execution on these data items. Accordingly an instruction cycle consists of following operations:
Types of bus cycles:
The total time required to fetch and execute an instruction is called an instruction cycle. An instruction cycle consists of one or more machine cycle.
The bus cycle of the 8086 microprocessor consists of at least four clock periods. These four time states are called T1, T2, T3 and T4. This group of states is called a MACHINE CYCLE.
One cycle of clock is called a state or t-state. Figure-1 shows the instruction cycle, machine cycle and T states
Timing diagram provide information about the changes in the conditions of the signals when some activity take place on the bus as a result of fetch, read/write and execution. Different peripherals in a system work only as per the timing diagram, so the knowledge of various timing parameters is one of the most important for the system designers.
The operation of fetch cycle or memory read cycle are same and is explained below and is shown in figure-2:
Operations During T1 state:
Operation during T2:
Operation during T3
Operation during T4:
This cycle indicate the completion of the read operation. During this cycle:
The memory write cycle differ from the memory read cycle in the following ways:
The I/O read write cycles also work similar to the memory read write cycle except that the M/IO’ signal goes low to indicate the I/O related operation on the bus. Other signal remain same as in memory read write cycles.