A bus cycle or machine cycle defines the sequence of events when the MPU communicates with an external device such as memory or I/O, which starts with an address being output on the system bus followed by a read or write data transfer.
An instruction cycle consists of :
A program consists of number of instructions which are stored in memory. These instructions are to be fetched from the memory and decoded to generate the necessary timing and control signals, an instruction may also contain data or a reference to a data that are also required to be read and then the CPU carries out the execution on these data items. Accordingly an instruction cycle consists of following operations:
- Instruction Fetch
- Read the operands
Types of bus cycles:
- Memory Read Bus Cycle – Read of code or data
- Memory Write Bus Cycle
- Input/output Read Bus Cycle
- Input/output Write Bus Cycle
The total time required to fetch and execute an instruction is called an instruction cycle. An instruction cycle consists of one or more machine cycle.
The bus cycle of the 8086 microprocessor consists of at least four clock periods. These four time states are called T1, T2, T3 and T4. This group of states is called a MACHINE CYCLE.
One cycle of clock is called a state or t-state. Figure-1 shows the instruction cycle, machine cycle and T states
Timing diagram provide information about the changes in the conditions of the signals when some activity take place on the bus as a result of fetch, read/write and execution. Different peripherals in a system work only as per the timing diagram, so the knowledge of various timing parameters is one of the most important for the system designers.
Memory Read Cycle:
The operation of fetch cycle or memory read cycle are same and is explained below and is shown in figure-2:
Operations During T1 state:
- The ALE is asserted which activates the latches and the 20-bit address is put on the address bus
- DT/R’ is asserted LOW for selecting the data direction from the transceivers
- M/IO’ is asserted HIGH to indicate memory operation
- BHE’ is made LOW for selecting a memory bank from banks of memory (odd and even bank)
Operation during T2:
- Address lines are inactive during this state
- A15-A0 goes in tri-state and are now reserved for carrying the data
- RD’ goes low at the end of T2 for memory read operation.
- DEN goes low for data reception
- 8086 samples the READY signal and if it is high T3, T4 are executed otherwise the wait state is inserted after T3
Operation during T3
- Data is put on the data bus (D15 – D0)
- Status signals still remain on the upper address lines A19 – A16.
Operation during T4:
This cycle indicate the completion of the read operation. During this cycle:
- RD’ goes high to indicate end of read operation. The data is read in the 8086 input latches
- DEN is asserted high to disable the transceivers.
Memory write cycle:
The memory write cycle differ from the memory read cycle in the following ways:
- The DT/R’ signal is asserted for the data transmission through the transceiver.
- The WR’ signal goes low during T2 and the data from the processor is placed on the data bus.
- During T3 the data is written on the memory.
- T4 marks end of the write operation so WR is asserted high, DEN goes low which disable the transceivers.
IO Read/ write cycles:
The I/O read write cycles also work similar to the memory read write cycle except that the M/IO’ signal goes low to indicate the I/O related operation on the bus. Other signal remain same as in memory read write cycles.