Instruction Format of 8086
The instructions in 8086 are 1 to 7 byte long depending on the addressing mode. The immediate byte may be 8 or 16 bit, and the displacement in an instruction can be 0 bits or 8 bits or 16 bits. The OP CODE and addressing mode designation may be 1 to 2 byte. Where the OPCODE use 2 byte, the first byte is OPCODE and the REG field of 2nd byte indicate the rest 3 bits of the OPCODE. The different bytes of the instruction are designated in the table below.

As seen above within the OP CODE there is a special 1 bit indicator such as W, D, S, V, Z. The V bit is used in the shift and rotate instructions to indicate number of shifts. The Z bit is used by the REP instruction.

1. W-bit: this bit in the opcode indicate whether the instruction operates on a byte (w=0) or  word (w=1).
2. D bit: Used to indicate that there are two operands. As one of the operand is always a register. D bit indicate whether register designated in REG field is source (D=0) or destination (D=1) when using sign extended 2’s complement this bit(D bit) is used as S bit.
3. S bit (sign extended s=1, s=0 normal representation) appears with W bit in the immediate to reg/mem add, sub and comp instructions and is assigned as:

8 bit operation – S:W=00
16 bit operation with 16 bit immediate operand- S:W= 01
16 bit operation with 8 bit sign extended immediate operand- S:W= 11
An instruction may use the operand as two registers or register to or from memory. The source and destination of the operand is indicated by the D field in the instruction and whether it is a byte or a word operation is indicated by the w field in the instruction. The register is identified by the REG / or R/M field. The 3-bit code of the register is as follows:

Segment Register Identification:

One of the two operand  is REG (register), the second operand which may be in REG or Memory may be specified in 32 different ways. The 2-bit filed named MOD and the 3-bit R/M field of the instruction format are used to specify the desired addressing modes.
The 2-bit field specifies on of the four different combinations as given below:

The combination of the 2-bit MOD field and 3-bit R/M field (total of 5-bits) specifies 36 different ways of specifying the 2nd operand. The second operand can be in a register or in memory. The effective address of the memory can be specified directly instruction, it can be in a register, or it can be the sum of one or two registers and a displacement. Table below shows the MOD and R/M codes for the 24 ways of specifying the effective address, the other 8 ways are when MOD=11 i.e. for the register-to-register transfer.

Encoding of 8086 Instructions
To code the 8086 instruction, we need to refer to the Appendix-B for the binary code of the instruction, then with the help of the figure above(which indicate the register codes and REG, we can encode the 8086 assembly language instructions to their equivalent binary.
Examples-1:
MOV SP, BX
Refering the discussion made above, the MOD field shold be 11 for reg-to-reg transfer, REG =100 for SP, and R/M =011 for BX register. d=1 indicating REG field to become as destination, w=1 for a word operation. And the binary code for MOV SP is 100010. Therefore the complete code is shown in the figure below.

thus the instruction MOV SP, BX is encoded as = 1000101111100011 = 8B E3h
whereas if we had the instruction as MOV BX, SP then, the coding will change because now the destination is BX, and the code would look like:
Example-2: MOV BX, SP

Thus the complete code is:
MOV BX, SP is encoded as = 1000100111011100 = 89DCh
Example-3:
We give two examples of the add instruction both of which add the content of BH and CL registers and put the result in CL; In the first  D=1, so REG field indicate the destination (here CL the code 001) and the R/M field as source register (BH with code 111), in the second D=0, REG field is the source register (BH with code 111) and R/M field is destination with code 001 for CL.

Example-4:

Example-5: Adding an immediate operand to AX ( A long Format) and A short Format