8086 Instruction Format-I

Instruction Format of 8086
The instructions in 8086 are 1 to 7 byte long depending on the addressing mode. The immediate byte may be 8 or 16 bit, and the displacement in an instruction can be 0 bits or 8 bits or 16 bits. The OP CODE and addressing mode designation may be 1 to 2 byte. Where the OPCODE use 2 byte, the first byte is OPCODE and the REG field of 2nd byte indicate the rest 3 bits of the OPCODE. The different bytes of the instruction are designated in the table below.

Byte OPCODE Here W=0/1 for 1 byte/2 byte operand; d = 0/1to show that designated register is src/dst. S bit used sign extended 2’s complement in which all bits of 2nd byte are same as MSB of 1st byte
1st Byte Opcode D or S w Opcode byte
2nd Byte Mode Reg R/M Addressing mode byte
3rd Byte

[optional]

low disp, addr, or data
4th Byte

[optional]

High  disp, addr, or data
5th Byte

[optional]

Low data
6th Byte

[optional]

High data

As seen above within the OP CODE there is a special 1 bit indicator such as W, D, S, V, Z. The V bit is used in the shift and rotate instructions to indicate number of shifts. The Z bit is used by the REP instruction.

  1. W-bit: this bit in the opcode indicate whether the instruction operates on a byte (w=0) or  word (w=1).
  2. D bit: Used to indicate that there are two operands. As one of the operand is always a register. D bit indicate whether register designated in REG field is source (D=0) or destination (D=1) when using sign extended 2’s complement this bit(D bit) is used as S bit.
  3. S bit (sign extended s=1, s=0 normal representation) appears with W bit in the immediate to reg/mem add, sub and comp instructions and is assigned as:

8 bit operation – S:W=00
16 bit operation with 16 bit immediate operand- S:W= 01
16 bit operation with 8 bit sign extended immediate operand- S:W= 11
An instruction may use the operand as two registers or register to or from memory. The source and destination of the operand is indicated by the D field in the instruction and whether it is a byte or a word operation is indicated by the w field in the instruction. The register is identified by the REG / or R/M field. The 3-bit code of the register is as follows:

REG W=0 byte operation W=1,  word operation
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

Segment Register Identification:

Segment Register Code
ES 00
CS 01
SS 10
DS 11

One of the two operand  is REG (register), the second operand which may be in REG or Memory may be specified in 32 different ways. The 2-bit filed named MOD and the 3-bit R/M field of the instruction format are used to specify the desired addressing modes.
The 2-bit field specifies on of the four different combinations as given below:

MOD Purpose
Case-1:
no displacement
00 The MOD field =00 indicate that the specified effective address in instruction contain no displacement. Example: MOV CX, [BX], indirect addressing and based-indexed addressing mode without displacement are in this category.
Case-2,
One byte  displacement
01 The register relative, and the relative based-indexed addressing mode with displacement of 1 byte are the instructions of this category. Examples are:
MOV CX, 47h[BX]
MOV CX, 47h[BX][SI]  etc.
Case-3: Two byte displacement 10 The register relative, and the relative based-indexed addressing mode with displacement of 2 byte are the instructions of this category. Examples are:
MOV CX, 1247h[BX]
MOV CX, 1247h[BX][SI]  etc.
Case-4:
Register-to-Register
11 MOD=11 specifies that the second operand also as one of the register.

The combination of the 2-bit MOD field and 3-bit R/M field (total of 5-bits) specifies 36 different ways of specifying the 2nd operand. The second operand can be in a register or in memory. The effective address of the memory can be specified directly instruction, it can be in a register, or it can be the sum of one or two registers and a displacement. Table below shows the MOD and R/M codes for the 24 ways of specifying the effective address, the other 8 ways are when MOD=11 i.e. for the register-to-register transfer.

MOD —>

00

01

10

11

Segment Register Used

R/M W=0 W=1
000 (BX)+(SI) (BX)+(SI)+D8 (BX)+(SI)+D16 AL AX DS
001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16 CL CX DS
010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16 DL DX SS
011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16 DL BX SS
100 (SI) (SI)+D8 (SI)+D16 AH SP DS
101 (DI) (DI)+D8 (DI)+D16 CH BP DS
110 D16 (BP)+D8 (BP)+D16 DH SI DS and SS
111 (BX) (BX)+D8 (BX)+D16 BH DI DS
Memory Addressing Register Addressing

Encoding of 8086 Instructions
To code the 8086 instruction, we need to refer to the Appendix-B for the binary code of the instruction, then with the help of the figure above(which indicate the register codes and REG, we can encode the 8086 assembly language instructions to their equivalent binary.
Examples-1:
MOV SP, BX
Refering the discussion made above, the MOD field shold be 11 for reg-to-reg transfer, REG =100 for SP, and R/M =011 for BX register. d=1 indicating REG field to become as destination, w=1 for a word operation. And the binary code for MOV SP is 100010. Therefore the complete code is shown in the figure below.

Instruction

OPCODE

MOD

Destination

Source/Destination

Displacement

Instruction OPCODE d W 11 REG R/M high Byte Low Byte
MOV SP, BX 100010 1 1 11 100 011

thus the instruction MOV SP, BX is encoded as = 1000101111100011 = 8B E3h
whereas if we had the instruction as MOV BX, SP then, the coding will change because now the destination is BX, and the code would look like:
Example-2: MOV BX, SP

Instruction

OPCODE

MOD

Source/
Destination

Displacement

Instruction OPCODE d w 11 REG R/M high Byte Low Byte
MOV BX, SP 100010 0 1 11 100 011

Thus the complete code is:
MOV BX, SP is encoded as = 1000100111011100 = 89DCh
Example-3:
We give two examples of the add instruction both of which add the content of BH and CL registers and put the result in CL; In the first  D=1, so REG field indicate the destination (here CL the code 001) and the R/M field as source register (BH with code 111), in the second D=0, REG field is the source register (BH with code 111) and R/M field is destination with code 001 for CL.

ADD Dest, Src ADD Src Reg, Dest Reg
ADD CL, BH ADD BH, CL
– – – – – -DW Mod/REG/r/m
W=0, 8 bit W=0, 8 bit Mod =11
00000010 11  001  111 02CF H 00000000 11 111 001 00F9 H
D=1, REG is destination 001=CL is destination D=0, REG is source 111=BH(src),
001=CL(dest)

Example-4:

ADD Dest, immediate

ADD Src Reg, Dest Reg

ADD 2345[BX][DI], 97FF ADD 2345[BX][DI], CL
– – – – – -dw Mod/REG/

r/m

Assume: BX=0892, DI=59A3, Disp=2345
W=1,
16 bit addition
MOD=10 16 bit Disp. Immediate

Operand

=97FF

W=1, 16 bit Mod =10 16 bitDisp
10000011 10 000 001 01000101

00100011

10010111

11111111

00000001 10 010 001 01000101

00100011

S=1, 000=part of OPCODE
001=is CX destination
D=0, REG is source 010=DX(src)
001=CL(dest)
4 5 2 3
EA=(BX)+(DI)+16bit Disp EA=(BX)+(DI)+16Bit Disp

Example-5: Adding an immediate operand to AX ( A long Format) and A short Format

ADD Dest, immediate

ADD Src Reg, immediate number

(ADD AX, 0123h )(ADD r/m, immediate data) ADD AX, 0123h
– – – – – -DW Mod/REG/r/m
S=0,W=1, for  16 bit Data MOD=11 16 bit immediate Data Machine Code W=1, 16 bit 16 bit imm. Data Machine Code
1000000w Mod000r/m 16 bit data 0000010w Data(L) data(H)
10000001 11  000 000 00100011
00000001
81C00123 00000101 00100011 00000001 050123
000=part of OPCODE
R/M 000 =AX destination
D=0, REG is source
In long format AX is explicitly indicated by R/M field In short form the AX is implied by the opcode
Updated: September 16, 2020 — 3:47 pm

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