AIM: Design a 4-bit Full adder using 1-bit full adder in VHDL using structural modelling

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fa1_4bit is

Port (

a : in  STD_LOGIC_VECTOR (3 downto 0);

b : in  STD_LOGIC_VECTOR (3 downto 0);

ci : in  STD_LOGIC;

s : out  STD_LOGIC_VECTOR (3 downto 0);

co : out  STD_LOGIC

);

end fa1_4bit;

architecture structural of fa1_4bit is

componentfullAdder is

Port (

a : in  STD_LOGIC;

b : in  STD_LOGIC;

ci : in  STD_LOGIC;

s : out  STD_LOGIC;

co1 : out  STD_LOGIC

);

end component;

signal carry : std_logic_vector(3 downto 1);

begin

X1: fullAdder PORT MAP (a(0), b(0), ci, s(0), carry(1));

X2: fullAdder PORT MAP (a(1), b(1), carry(1), s(1), carry(2));

X3: fullAdder PORT MAP ( a => a(2), b => b(2), ci=> carry(2), s=> s(2), co1=> carry(3));

X4: fullAdder PORT MAP ( a => a(3), b => b(3), ci=> carry(3), s=> s(3), co1=> co);

End structural;

 

Simulation of 4-bit Adder

 

 

AIM: Design a 4-bit Full adder using 1-bit full adder in VHDL using GENERATE Statement

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fa1_4bit is

Port (

a : in  STD_LOGIC_VECTOR (3 downto 0);

b : in  STD_LOGIC_VECTOR (3 downto 0);

ci : in  STD_LOGIC;

s : out  STD_LOGIC_VECTOR (3 downto 0);

co : out  STD_LOGIC

);

end fa1_4bit;

architecture Behavioral of fa1_4bit is

component FA1 is

Port (

a : in  STD_LOGIC;

b : in  STD_LOGIC;

ci : in  STD_LOGIC;

s : out  STD_LOGIC;

co1 : out  STD_LOGIC

);

end component;

signal carry : std_logic_vector(4 downto 0);

begin

carry (0) <= ci;

x1: for I in 0 to 3 GENERATE

X2: FA1 PORT MAP (

a(i), b(i), carry(i), s(i), carry(i+1)

);

end GENERATE;

co<= carry(4);

end Behavioral;

Simulation

Simulation of 4-bit Adder synthesized using Generate Statement

 

 

A-n-bit RCA is a simple chain of FAs. For N-bit adder, it consist N full adder  connected in series through their carry-in and carry-out ports, Each FA adds three bits A_i, B_i, and C_in to produce two bit ouput S_i and C_out bits.

Because the carry must propagate (ripple) through all the stages serially, this is the slowest adder architecture.

Roughly, the time required by the FA units to compute the carry out bit is two gate delays per FA units, thus total delay  in generating the final carry Cout is 2xN (2x number of FA) .

 

The values in Gray color (A₃A₂A₁A₀, B₃B₂B₁B₀  and C₀ )are given while in circles (C₄C₃C₂C₁ and S₃S₂S₁S₀ )are computed. The simplest multi-bit adder is the Ripple carry adder, shown below.

 

Figure: – 4-bit Ripple Carry Adder

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fa1_4bit is

Port (     a : in  STD_LOGIC_VECTOR (3 downto 0);

b : in  STD_LOGIC_VECTOR (3 downto 0);

ci : in  STD_LOGIC;

s : out  STD_LOGIC_VECTOR (3 downto 0);

co : out  STD_LOGIC);

end fa1_4bit;

 

architecture Behavioral of fa1_4bit is

signal carry : std_logic_vector(4 downto 0);

begin

carry (0) <= ci;

for I in 0 to 3 LOOP

s(i) <= a(i) xor b(i) xor carry(i);

carry (i+1) <= (a(i) and b(i)) or (b(i) and carry(i)) or (carry(i) and a(i));

end LOOP;

co<= carry (4);

end Behavioral;