## AIM: To Synthesize the BCD Adder and Generate the hardware and the waveform

## Objective:

- To understand basic process of addition
- To understand the VHDL syntax
- To Synthesize the BCD adder circuit
- To simulate verify the result

## Theory:

BCD numbers are represented as 4-bit code. With 4-bits, we can have 16 binary combinations of which only 10 ( 9 through 0) are valid BCD codes. Bit combinations 1010, 1011, 1100, 1101, 1110, 1111 are invalid in BCD representation.

While processing the BCD numbers, If the result of adding two BCD numbers fall in this range, the result is required to be adjusted to a correct value.

Check the result for a carry out or for result greater than 9.

If the result is less than 9, No adjustment factor is required

If result > 9 or there is a carry out of MSB: Adjestment is Required

*If Result >9 or carry into the MSB ; then add 6 to result*

*else note the result as correct*

## Block Diagram of BCD Addition Process

**Example:**

58 + 75; We will append zero on Most significant digit to indicate +ve number

058 = 0000 0000 0101 1000

075 = 0000 0000 0111 0101

—————————-

= 0000 0000 1100 1101

Adjust 0110 0110

——————————–

0000 0001 0011 0011

= 0 1 3 3

—————————————

### VHDL Code for BCD Adder

LIBRARY ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_unsigned.all;

Entity BCD_Adder is

Port (

x,y : in std_logic_vector(3 downto 0);

S : out std_logic_vector(4 downto 0)

);

End BCD_Adder;

architecture Behavioral of BCD_Adder is

Signal adjust :std_logic;

Signal sum :std_logic_vector ( 4 downto 0);

begin

Sum <= (‘0’ & x) + y;

Adjust <= ‘1’ when ((sum > 9 ) or sum(4)=’1′) else ‘0’;

S <= sum when (adjust =’0′) else Sum + 6;

end Behavioral;