entity DeMux is

Port (

I : in  STD_LOGIC;

S : in  STD_LOGIC_VECTOR (1 downto 0);

Y : out  STD_LOGIC_VECTOR (3 downto 0)

);

end DeMux;

architecture dataflow of DeMux is

begin

Y(0) <= I and (not S(1) ) and (not s(0));

Y(1) <= I and (not S(1) ) and (s(0));

Y(2) <= I and (S(1) ) and (not s(0));

Y(3) <= I and (S(1) ) and (s(0));

end dataflow;

  

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY DeMux_tb IS

END DeMux_tb;

ARCHITECTURE behavior OF DeMux_tb IS

— Component Declaration for the Unit Under Test (UUT)

COMPONENT DeMux

PORT(

I : IN  std_logic;

S : IN  std_logic_vector(1 downto 0);

Y : OUT  std_logic_vector(3 downto 0)

        );

END COMPONENT;

–Inputs

signal I : std_logic := ‘0’;

signal S : std_logic_vector(1 downto 0) := (others => ‘0’);

–Outputs

signal Y : std_logic_vector(3 downto 0);

BEGIN

— Instantiate the Unit Under Test (UUT)

uut: DeMux PORT MAP (

I => I,

S => S,

Y => Y

);

— Stimulus process

stim_proc: process

begin

— insert stimulus here

wait for 100 ns;

I <= ‘0’;

S<= “00”;

wait for 100 ns;

I <= ‘1’;

S<= “01”;

wait for 100 ns;

I <= ‘0’;

S<= “10”;

wait for 100 ns;

I <= ‘1’;

S<= “11”;

wait;

end process;

END;

 Simulation

 

 

 Behavioural Modelling of De-Mux

VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity DeMux is

Port (

I : in  STD_LOGIC;

S : in  STD_LOGIC_VECTOR (1 downto 0);

Y : out  STD_LOGIC_VECTOR (3 downto 0)

);

end DeMux;

architecture Behavioral of DeMux is

begin

process(S,I)

begin

if (S=”00″) then

Y <= “000”&I;

elsif (S=”01″) then

Y <= “00”&I&’0′;

elsif (S=”10″) then

Y <= ‘0’&I&”00″;

else

Y<= I&”000″;

end if;

end process;

end Behavioral;

SIMMULATION using ISIM