Design of Register using VHDL VHDL Lab by Ravinder Nath Rajotiya - August 12, 2019August 12, 20190 Share on Facebook Share Send email Mail Print Print Table of Contents Toggle AIM Objective:Theory:Different types of RegistersSynthesis of Registers in VHDLsimple registerregister with asynchronous resetregister with synchronous resetShift registers dataflowSISO Behaviour AIM Write VHDL programs for the following circuits, check the wave forms and the hardware generated register shift register Objective: The objective of this lab is to : revise the theory behind the working of the registers To learn VHDL coding for the registers Synthesize register using VHDL Verify the operation using functional Simulation using ISIM Theory: Registers are built using combination of flip-flops. They are the internal storage units for any digital systems. They are of different sizes and are used for temporary storage of memory address(MAR), data to be written to main memory(write buffers), data to be read from memory (read buffers), status condition of an ALU (Flag/ status register). Different types of Registers Serial-in-serial-out shift register Serial-in-parallel-out shift register Parallel-in-Serial-out shift register parallel-in-parallel-out shift register bidirectional shift register Synthesis of Registers in VHDL simple register A simple 8-bit register in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity register_8bit is Port ( D : in STD_LOGIC_VECTOR(7 downto 0); CLK : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(7 downto 0) ); end register_8bit; architecture Behavioral of register_8bit is begin process(CLK, D) begin if ( CLK’event and CLK=’1′ ) then Q<= D; end if; end process; end Behavioral; register with asynchronous reset Asynchronous reset: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity register_8bit is Port ( D : in STD_LOGIC_VECTOR(7 downto 0); reset : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(7 downto 0) ); end register_8bit; architecture Behavioral of register_8bit is begin process(CLK, D) begin if reset=’0’ then Q <= “00000000”; elsif ( CLK’event and CLK=’1′ ) then Q <= D; end if; end process; end Behavioral; register with synchronous reset Synthesis of Register with Synchronous reset library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity register_8bit is Port ( D : in STD_LOGIC_VECTOR(7 downto 0); reset : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(7 downto 0) ); end register_8bit; architecture Behavioral of register_8bit is begin process begin wait until CLK’event and CLK=’1’; if (reset =’0’) then Q <= “00000000”; elsif (CLK’event and CLK=’1′) then Q <= D; end if; end process; end Behavioral; Shift registers dataflow Synthesis of Shift Registers using VHDL Shift registers are used to shift the contents of the register left or right by 1 bit. They are generally used for binary multiplication and division. Shift Left Operation Shift Right Operation Q(0) Q(1) — – Q(n-1) Q(0) Q(1) – – Q(n-1) Shift register using concurrent style of modelling library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity shift_reg is Port ( D : in STD_LOGIC; RESET : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0) ); end shift_reg; architecture Behavioral of shift_reg is signal tmp : std_logic_vector(3 downto 0); begin process(CLK,tmp, RESET) begin if RESET = ‘1’ then tmp<= “0000”; elsif (clk’event and clk=’1′) then tmp(3) <= tmp(2); tmp(2) <= tmp(1); tmp(1) <= tmp(0); tmp(0) <= D; end if; Q <= tmp; end process; end Behavioral; SISO Behaviour Behavioural Modlling of serial in serial out left shift register entity shift_behave is Port ( D : in STD_LOGIC; RESET : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0) ); end shift_behave; architecture Behavioral of shift_behave is signal tmp : std_logic_vector(3 downto 0):=”0000″; begin process(CLK,tmp, RESET) begin if RESET = ‘1’ then tmp<= “0000”; elsif (clk’event and clk=’1′) then for I in 3 downto 1 LOOP tmp(i) <= tmp(i-1); end LOOP; tmp(0)<= D; end if; Q <= tmp; end process; end Behavioral; Share on Facebook Share Send email Mail Print Print