An adder is a combinational circuit that adds multi-bit (two or more).

## Different types of adders are:

2. Full Adder : A combinational circuit that adds 2-bits and a carry from the previous stage of addition.
5. Serial Adder: An adder that takes the serial data inputs, computes the sum and carry for bit Ai, Bi, Ci produces Si; each time an addition is performed the sum bit shifted in a shifter. The content of shift register gives the Sum output.

A half adder circuit is a logic circuit that adds two bits (logically one bit and a carry from the previous stage) and generates a sum and a carry as the output. The functional or the truth table of the half adder is given below:

 Inputs Outputs A B Carry Sum 0 0 0 0 0 1 0 1 (A’B) 1 0 0 1 (AB’) 1 1 1 (AB) 0

The SOP equations for the SUM and the Carry are written below:
Sum=AB’ + A’B
Carry = AB
Logic circuit of the half-adder is given below Usage:
The HA is used in limited applications like incrementer

Exercise: Implement a Half subtractor circuit.

A Full Adder (FA) adds three bits. The three input bits are two bits of the two numbers and the third bit is the carry-in from the previous stage.  and generates a sum and carry bit. The truth table of the full-adder is shown below:

 C B A Sum Carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

The SOP equations for the output variable Sum and the Carry are given below:
Sum= C’B’A + C’BA’ + CB’A’ + CBA

Carry= C’BA + CB’A + CBA’ + CBA

Simplification of the above equation.

Sum =     A(C’B’ + CB) + A'(C’B + CB’)

=          A    ⊕      B     ⊕       C

Carry     =     C’BA + CB’A + CBA’ + CBA

=     A (C’B + CB’) + CB(A’ + A)

=     A ( B  ⊕   C)  + BC

The logic circuit diagram is as follows: A Full Adder is capable of adding only two single digit binary number along with a carry input. But in practical we need to add binary numbers which are much longer than just one bit.
To add two multi-bit binary numbers we need to cascade as many full-adders. Carry in Cin to first stage is reset to zero for 1st stage addition. For subsequent stages, the Cout of one stage acts as the Cin of the next stage.

Example: Figure: Parallel/Ripple carry/Carry Propagate Adder example

The block diagram of the two 4 bit parallel adder circuit is shown in figure-3 Now let’s dry-run the addition process using the above block diagram using two 4-bit numbers

A  =   1  1  0  1                       (addend)

B  =   1  0  1  0                      (augend)

——————————————————-

A+B   =  1 0 1  1  1

Figure below shows the internal logic of each block of the binary adder The decimal addition is performed by using BCD codes for the decimal numbers. Since the 4 bits are required to represent decimal digits, however with 4 bits we can have 16 combinations. Of these 16 combinations, the first 10 combinations (0 through 9) are the valid ones and the rest 6 binary combinations 1010, 1011, 1100, 1101, 1110, 1111 are invalid combinations in BCD. Example: BCD the adding of 9 and 6 :

9   =  1001

6   =  0110

————————————————

9+6      =  1111

Result > 9 so,Add 6      0110

————————————————-

1 0101

Result      0001 0101 =  1510

——————————————————-

The valid BCD codes are the codes for digits 9 through 0 and all all other 4-bit combinations like 1010, 1011, 1100, 1101, 1110, 1111 are invalid and not allowed. Table in figure below shows the valid and invalid outputs. The outputs (Gr9) marked ‘0 are valid outputs and those marked ‘1’ in truth table are invalid outputs.

The equation for Gr9 is :

Gr9 =  S8S4 + S2S1

The equation Gr9 will  turn to be true whenever the sum exceeds 9 i.e. when output becomes one of these six invalid BCD combinations (1010, 1011, 1100, 1101, 1110, 1111). To correct the result,we need to add 6 to this invalid result. Also if a carry out results then also we add 6 to correct the result.

The output logic equation for doing adjustment is :

D=Co  + S8S4 + S2S1

Figure below shows the complete design process of BCD Adder A serial adder is a sequential circuit that adds two multi-bit numbers in a serial fashion. A pair of bits and a carry-in is provided at a time to the FSM. The result and the inputs are then shifted one bit to the right and another set of inputs provided and so on. A detailed design process will be provided in design of sequential circuit.

Figure below shows the block diagram of the serial adder.  Figure : Example and Process in Serial Addition

As the name indicate, carry look ahead adder pre-computes the carry. Careful analysis of the truth table for carry output reveals that carry will be generated when both A and B input are held high (shown in red). The entry in green color suggest that a carry propagate Figure: Carry generation in CLA

Equation for              Ci+1 =  (A ⊕  B).Ci  + A.B

here:

Gi = AiBi where G is called carry generator

Pi = Ai ⊕ Bi where P is called carry propagator

The carry equation at different stage are:

C1 = C0 (A0 ⊕ B0) + A0B0              = C0 P0 + G0

C2 = C1 (A1 ⊕ B1) + A1B1             = C1 P1 + G1

C3 = C2 (A2 ⊕ B2) + A2B2             = C2 P2 + G2

C4 = C3 (A3 ⊕ B3) + A3BR         =C3 P3 + G3

The following equations shows that the carry in of any stage depends only on the bits being added in previous stages and the carry bit which was provided in the beginning-

• C1 = C0P0 + G
• C2 = C0P0P1 + G0P1 + G1
• C3 = C0P0P1P2 + G0P1P2 + G1P2 + G2
• C4 =C0P0P1P2P3 + G0P1P2P3 + G1P2P3 + G2P3 + G3

## Exercise

1. Write the SOP equation for a Half Subtractor and draw the logic circuit.
2. Write the SOP equation for a Half Subtractor and draw the logic circuit.
3. Study the diagram of a half adder and half subtractor and draw a common circuit that can perform the function of both the half subtraction and half adder
4. Implement a Half Adder and Full Adder using all NAND gates
5. Why is necessary to correct the sum by adding 6 with the sum output in a BCD addition.

## Quiz

1. For a binary half subtrator having two inputs A and B, the correct set of logical expression for the output D=(A minus B) and X(borrow) are:

(a). D=AB + (AB)’ ; X = A’B

(b). D=(AB)’ + AB’; X= A’B

(c). D=A’B + AB’; X= A’B

(d). D= AB +A’B’; X= A’B

2. Which one of the following difference and Borrow equation are correct for a Full subtractor.

(a). D= x ⊕ y + z; B= x’y +yz + zx’

(b). D= x ⊕ y ⊕ z; B= xy +yz + zx

(c). D= x ⊕ y ⊕ z; B= x’y +yz + zx’

(d). a and c both

3. The sum output of a half adder is given by

(a). S=AB(A+B)’

(b). S= (A+B)(AB)’

(c). S=(A+B)(AB)

(d). S=(A’+B’)(A’B)

4.  The Carry Generate and Carry Propagate function of the look ahead carry adder is

(a). CG = A + B,        CP = A ⊕ B

(b). CG = A ⊕ B        CP = A + B

(c). CG =  AB             CP = A ⊕ B

(d). CG = AB              CP = A + B

5. If we have inputs as A, B and C and outputs S and D. We are given that S= A ⊕ B ⊕ C  and D= BC + A’B + A’C. Which of the circuit is represented by it.

(a). 4-bit adder giving X + Y

(b). 4-bit subtractor giving X – Y

(c). 4-bit subtractor giving  Y – X

(d). 4-bit adder giving X + Y + S

6. For a full subtractor, which of the combination will give the difference?

(a). [ { A ⊕ B){(A ⊕ B)bi}’}’. {bi.( ((A ⊕ B)bi)’}’]’

(b). [B.(AB)’. (bi.(A ⊕ B))’]’

(c). (A’ + B’)’ + (b’ +(A ⊕ B)’)’

(d). None of the above

7. A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND and NOR gates only. Assuming that all inputs are available in complemented  an un-complemented form and the delay of each gate is one time unit. What is the overall propagation delay of the adder? Assume that the carry network has been implemented  using two-level AND-OR logic.

(a).  4 time units

(b). 6 time units

(c). 10 time units

(d).  12 time units

9. In a look ahead carry generator, the carry generate function Gi and the carry propagate function Pi for input A and B is given by: Pi = A ⊕ B and Gi = A.B

The expression for the sum bit Si and the carry bit Ci+1 of the carry look ahead adder is given by S= Pi ⊕ Ci   and  Ci+1 = Gi + PiCi where Ci is the input carry.

Consider a two level logic implementation of the look ahead carry generator. Assume that all Pi and Gi are available  fr the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND and OR gate needed to implement the look-ahead carry generator for a 4-bit adder with S3S2S1S0 and the C4  as the output are respectively.

(a).  6, 3

(b).  10, 4

(c).  6, 4

(d).  10, 5

Updated: August 17, 2019 — 5:37 pm