Operators in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 13, 2021May 13, 20210 OPERATORS VHDL has a wide set of operators. These are specific to the data types, all operators do not operate on every data types. They are further divided into groups of the same precedence level (priority).Table below shows all operators as per their precedance low to high, row-1 has the lowest priority whereas operators of row-7 has the highest priority. Within each row the priority is from left to right with the leftmost having highest priority. Class Operator Precedence Low high Same Operator Precedence (Applied Left –to-Right) 1. Logical operators and or nand nor xor xnor 2. Relational operators = /= < <= > >= 3. Shift operators sll srl sla sra rol ror 4.Addition operators + = & 5. Unary operators + - 6. Multiplying op. * / mod rem 7. Miscellaneous op. ** abs not The order of precedence is the highest for the operators of class 7, followed by class 6 with the lowest precedence for class 1. Unless parentheses are
Access and File types in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 13, 2021May 14, 20210 Access Type: Access type allows to manipulate data, which are created dynamically during simulation and which exact size is not known in advance. Any reference to them is performed via allocators, which work in a similar way as pointers in programming languages. Simplified Syntax access subtype_indication type identifier; Here, the subtype_indication denotes the type of an object designated by a value of an access type. It can be any scalar, composite or other access type. File type is not allowed here. Variables are only the objects allowed to be of the access type. The default value of an access type is null. NULL designates no object at all. Allocators has to be used to assign any other value to an object of an access type. The access type allows to create recursive data structures
Array and Records in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 13, 2021May 13, 20210 Composite Data Type: In addition to predefined type, VHDL also allow us to use array and record types in our VHDL designs. This can provide us with a more structured design which is easier to maintain. These are of two types: Array Record: records are like structures in C language. They allow us to use different types Array: An array is a collection / group of elements of the same type as a single object. Array can be of any type In VHDL. Array can be one dimension, two dimension and multi dimension. Syntax: type <type_name> is array (<range> ) of <type> ; the <range> field in the above example can be built using the downto and to VHDL keywords Type of Arrays Constrained type array Unconstrained
Enumeration Type Digital Design using VHDL by Ravinder Nath Rajotiya - May 11, 2021May 11, 20210 Enumeration Type: Enumeration type is used when it is represent values that are required for a specific operation. All values in an enumeration are user defined and cannot be any one from predefined types. These values may be character literals or named identifiers. For examples we can use values as ‘0’,’1’…..’a’,’b’,c’……..ADD, SUB, MUL……. Note here that we cannot use the numeric values such as 0, 1 etc VHDL will give error during synthesis, but we are to use them as character literals as ‘0’ , ‘1’ . Syntax: TYPE TYPE_NAME is (value{,value}); BIT Type: A bit type object can hold value ‘0’ or ‘1’. It is an enumerate type defined in the std library. The syntax of BIT type as defined in std library
Data Types in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 10, 20210 Data Types in VHDL The syntax of object declaration as studied in the previous chapter is again revisited. Object_class Object_name : Object_data_type[:= Initial_value]; The essential component of the above declaration is object class and data type. Whereas the class signifies the class/category (signal, variable, constant, file) to which the object belongs, the data type gives an idea of the type (bit, Boolean, std_logic, integer etc.) -of the values an object may take and the value from a set of the values that an object may be assigned. Every given data type supports some specific operations for the object for example data type bit supports logical and arithmetic operations but std_logic (as given in std-logic_1164) does not support arithmetic operation. If arithmetic operation on std_logic