Data Objects in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 10, 2021May 10, 20210 Data Object: Every VHDL code needs some identifiers as the name of either the keyword or user-defined name as stated above. Those identifiers or elements which are used to hold some values are viewed in VHDL as a so called object or data object. Each data object of a VHDL program must be declared prior to its use. A data object holds a value of some specified type. The declaration syntax of a data object is : OBJECT_CLASS identifier [,identifier ...] : TYPE [:=value]; In the above syntax, an identifier is the name specified to the object, and type is the permitted kind of value that a object can have. Object class specifies the class of the object which may be classified
Identifiers in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 10, 2021May 10, 20210 Identifiers in VHDL An identifier represent a token in VHDL. VHDL has token in the form of reserve word and user defined word. Further, identifier may be : Basic identifier Extended identifiers. Basic Identifiers: These are used to define user defined names and following rules applies to the valid basic identifiers: The valid character set in The first letter of an identifier is always an alphabet (‘a’…’z’ or ‘A’…..’Z’) and digits 0 – 9. the first letter cannot be a special character or digit or underscore The last letter may be a letter or a digit but cannot be an underscore Double underscore anywhere is not permitted Graphical character/special symbols are not permitted Keywords cannot be used as basic
VHDL Modeling Styles Digital Design using VHDL by Ravinder Nath Rajotiya - May 10, 2021May 10, 20210 VHDL Modeling Styles Concurrent or Dataflow Modelling: The Dataflow description is built with concurrent signal assignment statements. Each of the statements can be activated when any of its input signals changes its value. This is shown with the help of a 2-to-4 decoder. The output of the decoder is used to illuminate one of the four LEDs. The entity is given in the following code in VHDL Entity Decoder_bcd is Port ( A, B : in std_logic; O : out std_logic_vector( 3 downto 0) ); End entity Decoder_bcd; architecture Dataflow of Decoder_bcd is begin O(3) <= A and B; O(2) <= A and (not B); O(1) <= (not A) and B; O(0) <= (not A) and (not B); end Dataflow; All the four statements here are executed concurrently and each of them is activated individually when any of its input signals changes its value. 2. Behaviour (Functional) Model: The architecture body describes
Structure of VHDL Code Digital Design using VHDL by Ravinder Nath Rajotiya - May 10, 2021May 13, 20210 Lecture-3 Structure of VHDL Code A general structure of the VHDL code is shown in figure Structure of VHDL program --Library clause is used to declares the name as a pre-defined/or user-defined library. LIBRARY<library_Name>; -- Library IEEE will be used almost in every code -- we need to import one or more packages from different libraries as given below USE<library_name>.<package_name>.ALL; --this is the format for importing packages USEIEEE.STD_LOGIC_1164.ALL; -- this package is required for bit, std_logic, --& std_logic_vector declarations and some related operations -- arithmetic functions with Signed or Unsigned values USEIEEE.NUMERIC_STD.ALL; -- then we declare the entity ENTITY<entity_name>IS --the entity can have generic for constant declaration and input output port declaration GENERIC( generic_name : generic_type : generic_value); PORT ( <signal_name> : mode <type>; <signal_name> : mode <type> := default_value; <signal_name> : INOUT<type>; <signal_name>
History and Features of VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 10, 20210 History and Features of VHDL The Requirement The development of VHDL was initiated in 1981 by the United States Department of Defence to address the hardware life cycle crisis. The cost of re-procuring electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology. Standardization The standardization process for VHDL was unique in that the participation and feedback from industry was sought at an early