PIC Interrupts Introduction: PIC16F877 has 14 interrupt sources. The following registers are used for setting the interrupt and checking the status of the interrupt. These are INTCON Register (04 registers, duplicated in each bank addresses 0Bh, 8Bh, 10Bh, 18Bh) PIE1 Register (Address 8Ch ) PIR1 Register (Address 0Ch) PIE2 Register (Address 8Dh) PIR2 Register( Address 0Dh) Figure-1 illustrates how the request from the interrupt source is communicated to the CPU.   Table-1 shows the various sources of interrupts, and the registers used to enable the interrupts and the status flags Type   Interrupt Register SFR Address REGISTER INTERRUPT ENABLE BIT INTERRUPT FLAG BIT STATUS FLAG REGISTER Status(Flag) Register SFR Address Global 0Bh  / 8Bh/10Bh, 18Bh INTCON GIE Peripheral 0Bh  / 8Bh/10Bh, 18Bh INTCON PEIE Timer0 0Bh  / 8Bh/10Bh, 18Bh INTCON T0IE T0IF INTCON 0Bh  / 8Bh External 0Bh  / 8Bh/10Bh, 18Bh INTCON INTE INTF INTCON 0Bh /  8Bh PortB 0Bh  / 8Bh/10Bh, 18Bh INTCON RBIE RBIF INTCON 0Bh  /8Bh Parallel Slave Port Read/Write   8Ch PIE1 PSPIE PSPIF PIR1 0Ch ADC 8Ch PIE1 ADIE ADIF PIR1 0Ch USART

Memory Organization: The internal block diagram iPIC16F87x in figure1 shows the three memory block the program memory, EEPROM data memory and the RAM; some controller like 16C61 has only two blocks of memory program memory and data memory.  As shown the program memory and the data memory  use separate buses for concurrent access of these memory. 16F877 has 8K x 14 bit word memory and 8 byte stack organization. Figure-1 shows the program and the stack memory map organization. Whereas the program memory is used to store the application program, the stack memory is used only for storing return addresses and some critical data that is required to be saved while transferring the contol of the program such as call to subroutine

PIC Instruction Set: PIC is RISC based architecture supporting only 35 instructions. These instructions can be classified in the following categories: 1. Register File Operations: Byte oriented operations Bit oriented operations Literal and control operations 2. Based on Functions Data Transfer Operations Arithmetic Operations Logical Operations Shift and Rotate Branch and Return These instructions are shown in the Byte-Oriented Operations Mnemonic Description Cycles 14-bit OPCode Status Affected ADDWF  f,d Add W and F 1 0 0111 dfff ffff C, DC, Z ANDWF   f,d Logical AND W with f 1 000101 dfff ffff Z CLRF       f Clear f 1 0000011fff ffff Z CLRW Clear W 1 00 0001 0xxx xxxx Z COMF     f,d Complement f 1 00 1001 dfff ffff Z DECF      f,d Decrement f 1 00 0011 dfff ffff Z DECFSZ  f,d Decrement f and skip if zero 1(2) 00 1011 dfff ffff INCF      f,d increment 1 00 1010 dfff ffff Z INCFSZ  f,d Increment f, and skip if zero 1(2) 00 1111 dfff ffff IORWF   f,d Inclusive OR W with f 1 00 0100 dfff ffff Z MOVF    f,d Move f 1 00 1000 dfff ffff Z MOVWF   f Move W to