PIC Interrupts

PIC Interrupts

Introduction:

PIC16F877 has 14 interrupt sources. The following registers are used for setting the interrupt and checking the status of the interrupt. These are

  • INTCON Register (04 registers, duplicated in each bank addresses 0Bh, 8Bh, 10Bh, 18Bh)
  • PIE1 Register (Address 8Ch )
  • PIR1 Register (Address 0Ch)
  • PIE2 Register (Address 8Dh)
  • PIR2 Register( Address 0Dh)

Figure-1 illustrates how the request from the interrupt source is communicated to the CPU.

 

Table-1 shows the various sources of interrupts, and the registers used to enable the interrupts and the status flags

Type

 

Interrupt Register SFR Address REGISTER INTERRUPT ENABLE BIT INTERRUPT FLAG BIT STATUS FLAG REGISTER Status(Flag) Register SFR Address
Global 0Bh  / 8Bh/10Bh, 18Bh INTCON GIE
Peripheral 0Bh  / 8Bh/10Bh, 18Bh INTCON PEIE
Timer0 0Bh  / 8Bh/10Bh, 18Bh INTCON T0IE T0IF INTCON 0Bh  / 8Bh
External 0Bh  / 8Bh/10Bh, 18Bh INTCON INTE INTF INTCON 0Bh /  8Bh
PortB 0Bh  / 8Bh/10Bh, 18Bh INTCON RBIE RBIF INTCON 0Bh  /8Bh
Parallel Slave Port Read/Write

 

8Ch PIE1 PSPIE PSPIF PIR1 0Ch
ADC 8Ch PIE1 ADIE ADIF PIR1 0Ch
USART Receive

 

8Ch PIE1 RCIE RCIF PIR1 0Ch
USART Tx

 

8Ch PIE1 TXIE TXIF PIR1 0Ch
Synchronous Serial Port

 

8Ch PIE1 SSPIE SSPIF PIR1 0Ch
CCP1 8Ch PIE1 CCP1IE CCP1IF PIR1 0Ch
TMR2 to PR2 Match

 

8Ch PIE1 TMR2IE TMR2IF PIR1 0Ch
TMR1 Overflow Interrupt 8Ch PIE1 TMR1IE TMR1IF PIR1 0Ch
CCP1 8Dh PIE2 CCP2IE CCP2IF PIR2 0Dh
Bus Collision

 

8Dh PIE2 BCLIE BCLIF PIR2 0Dh
EEPROM Write Operation

 

8Dh PIE2 EEIE EEIF PIR2 0Dh

 

Table below shows a summary of the registers being used for configuring the interrupts and to know their status. INTCON, PIE1, PIE2 are used to configure the interrupts whereas PIR1, PIR2 are the status or the flags for these interrupt, INTCON also shows the status for three interrupts RBIE, INTE, and TOIE interrupts

 

Bank Address Name D7 D6 D5 D4 D3 D2 D1 D0 Value on: POR, BOR
0 / 1/2/3 0Bh / 8Bh/10Bh/18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x
0 0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 00000000
0 0Dh PIR2 EEIF BCLIF CCP2IF -r-0 0–0
1 8Ch PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 00000000
1 8Dh PIE2 EEIE BCLIE CCP2IE -r-0 0–0

The following paragraphs discuss the different register setting for interrupts

INTCON Register

The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts.

D7 D6 D5 D4 D3 D2 D1 D0
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
Global Intr enable Peripheral Interrupt Enable bit TMR0 Overflow Interrupt Enable bit RB0/INT External Interrupt Enable bit RB Port Change Interrupt Enable bit TMR0 Overflow Interrupt Flag bit RB0/INT External Interrupt Flag bit RB Port Change Interrupt Flag bit
1-Enable

0-disable

1-Enables

0-Disables

1 Enable TMR0 intr

0 Disable

1 enable

0 disable

1 enable

0 disable

1 TMR0 has overflowed 1 interrupt occured 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software).
0 = None of the RB7:RB4 pins have changed state

 

OPTION_REG

The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB.

 

D7 D6 D5 D4 D3 D2 D1 D0
RBPU’ INTEDG T0CS T0SE PSA PS2 PS1 PS0
PORTB Pull-up Enable bit Interrupt Edge Select bit TMR0 Clock Source Select bit

 

TMR0 Source Edge Select bit Prescaler Assignment bit

 

Prescaler Rate Select bits
1 Disable

0 enable by port latch

1 Interrupt on rising edge of RB0/INT

0 on falling edge

1 =Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
 Note:There is only one prescaler available which is mutually exclusively shared between the T0 module and the WDT Timer. When assignment for the T0 module , then it is not for the Watchdog Timer and vice versa. This prescaler is not accessible but can be configured using PS2:PS0 bits of OPTION_REG.

 

PIE1 Register

The PIE1 register contains the individual enable bits for the peripheral interrupts.

 

D7 D6 D5 D4 D3 D2 D1 D0
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
Parallel Slave Port Read/Write Interrupt Enable bit A/D Converter Interrupt Enable bit USART Receive Interrupt Enable bit

 

USART Tx Interrupt Enable bit

 

Synchronous Serial Port Interrupt Enable bit CCP1 Interrupt Enable bit TMR2 to PR2 Match Interrupt Enable bit TMR1 Overflow Interrupt Enable bit
1 Enable

0 Disable

1 Enable

0 Disable

1 Enable

0 Disable

1 Enable

0 Disable

1 Enable

0 Disable

1 Enable

0 Disable

1 Enable

0 Disable

1 Enable

0 Disable

 

PIR Register

PIC microcontroller has two interrupt flag registers these are PIR1 and PIR2 registers. These flags are set or reset depending on the status of interrupt. Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. These registers are explained in the following paragraphs.

 

D7 D6 D5 D4 D3 D2 D1 D0
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
Parallel Slave Port Read/Write Interrupt Flag bit A/D Converter Interrupt Flag bit USART Receive Interrupt Flag bit USART Transmit Interrupt Flag bit Synchronous Serial Port (SSP) Interrupt Flag bit CCP1 Interrupt Flag bit TMR2 to PR2 Match Interrupt Flag bit TMR1 Overflow Interrupt Flag bit

 

‘1’ READ/WRITE OPERATION IS COMPLETED

‘0’ Not Completed

1-A/D conversion complete

‘0’ AD operation not completed

1 =USART receive buffer is full

‘0’-Rx buffer empty

1 =USART Tx buffer is empty

‘0’-USART Tx buffer full

1 = TMR2 to PR2 match occurred

‘0’ No match

1 = TMR1 register overflowed(must be cleared in s/w)

‘0’ no overflow

 

 PIE2 Register

The PIE2 register contains the individual enable bits forthe CCP2 peripheral interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt.

 

D7 D6 D5 D4 D3 D2 D1 D0
CMIE EEIE BCLIE CCP2IE
Comparator Interrupt Enable bit EEPROM Write Operation Interrupt Enable bit Bus Collision Interrupt Enable bit CCP2 Interrupt Enable bit
1 = Enables

‘0’ Disable

1 = Enable

‘0’ Disable

1 = Enable

‘0’ Disable

1 = Enable

‘0’ Disable

 

PIR2 Register

The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt.

D7 D6 D5 D4 D3 D2 D1 D0
CMIF EEIF BCLIF CCP2IF
Comparator Interrupt Flag bit EEPROM Write Operation Interrupt Flag bit Bus Collision Interrupt Flag bit

 

CCP2 Interrupt Flag bit

 

1 = The comparator input has changed (must be cleared in software)

‘0’ No change

‘1’ operation complete

‘0’ operation not yet completed

‘1’ A bus collision has occurred in the SSP when configured for I2C Master mode

‘0’ No collision

 

Updated: September 8, 2020 — 11:09 pm

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