Design all gates using VHDL


Experiment-1:

AIM : Design all gates using VHDL

Objectives:

The objective of this experiment is to:
i. To revise the working of various logic gates
ii. To learn the VHDL coding
iii. To simulate for functional verification
iv. To implement on CPLD / FPGA

Symbols and Truth Table of Logic Gates:

Symbol Name Symbol Truth Table Logic Function
NOT Gate / Inverter

 

 

Input Output
A Y
0

1

1

0

 

 

 

Y = NOT A

Y = A’

OR Gate

 

 

Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

 

 

 

Y = A OR B

Y = A  +   B

NOR Gate  

 

 

Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

 

 

 

Y = A NOR B

Y = (A + B)’

Y = NOT ( A OR B)

 

 

AND Gate

 

 

Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

 

 

 

Y = A AND B

Y = A.B

NAND Gate

(Universal Gate)

 

 

 

Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

 

 

 

Y = A NAND B

Y =  (A.B)’

 

XOR Gate

(Universal Gate)

 

 

Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

 

 

 

 

Y = A’B + AB’

Y = A XOR B

Y = A ⊕ B

 

VHDL Code to Design Logic Gates

NOT Gate

NOT Gate Design

NOT Gate
Inverter

 

 

 

 

Function:

A NOT gate produces the complement of the input.

Modeling Style

Dataflow Modeling: This style uses the logic equation Y = A’

Behavioral Modeling: This style of modeling uses the algorithm for modeling. The behavior of a NOT gate states that the output is HIGH ‘1’ when input applied is LOW ‘0’ and vice versa.

VHDL Code for Synthesizing NOT Gate

Dataflow Architecture Behavioral Architecture
Library IEEE;

use IEEE.std_logic_1164.all;

entity NOT1 is

port (

A : in STD_LOGIC;

Y : out STD_LOGIC

);

end NOT1;

Architecture dataflow of NOT1 is

Begin

Y <= NOT A;

end dataflow;

 

Library IEEE;

use IEEE.std_logic_1164.all;

entity NOT1 is

port  (

A : in STD_LOGIC;

Y : out STD_LOGIC

);

end not1;

Architecture behave of NOT1 is

begin

process (X)

begin

if (x=’0′) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of Inverter (NOT Gate)

OR Gate

 

OR Gate

 

 

Function:

An OR gate is all pass gate. It produces a high output when any or all inputs are high.

Modeling Style

Designing Data-flow Modeling: Use Logic Equation: i. Y = A +

Designing Behavior Modeling : The behavior of the circuit is that when any or all                                                              the is HIGH ( ‘1’) the output is HIGH (‘1’), else the                                                            output is LOW ‘0’

VHDL Code for Synthesizing OR Gate

Dataflow Designing of OR Gate Behavioral Modeling of OR Gate
Library IEEE;

use IEEE.std_logic_1164.all;

entity OR2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC

);

end OR2;

 

architecture behav1 of OR2 is

begin

Y <= A or B;

end behav1;

Library IEEE;

use IEEE.std_logic_1164.all;

entity OR2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC

);

end OR2;

architecture behav2 of OR2 is

begin

process (A, B)

begin

if (A = ‘0’ and B= ‘0’) then

Y <= ‘0’;

else

Y <= ‘1’;

end if;

end process;

end behav2;

Simulation of OR Gate

AND Gate

AND Gate

 

 

Function:

An AND gate produces high output when all inputs are high

Modeling Style

Data flow/Concurrent Modeling: Make use of logic equation Y <= A.B

Sequential/Behavior Modeling : Make use of behavior algorithm i.e. AND gate produces a HIGH ‘1’ output when both A and B are high ‘1’, otherwise the output is LOW ‘0’

VHDL Code for Synthesizing AND Gate

Dataflow /Concurrent Modeling Behavior Modeling
Library IEEE;

use IEEE.std_logic_1164.all;

entity AND2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y: out STD_LOGIC

);

end AND2;

architecture dataflow of AND2 is

begin

Y <= A and B;

end dataflow;

 Library IEEE;

use IEEE.std_logic_1164.all;

entity AND2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC

);

end AND2;

architecture behave of AND2 is

begin

process (A, B)

begin

if (A=’1′ and B=’1′) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of the AND Gate

NOR Gate

Symbol

 

 

Function

A NOR gate is an OR followed by an INVERTER. It produces a high output when all inputs are low

Modeling Style

Dataflow /Concurrent Modeling: This style use the logic equations in design. For a NOR the logic eqn is Y = (A + B)’

Behavior / Sequential Modeling : This style of modeling for NOR Gate use the behavior /algorithm to describe the operation. For a NOR Gate the output is high when both A and B are LOW ‘0’  otherwise the output is HIGH ‘1’

VHDL Code for Synthesizing NOR Gate

Dataflow/Concurrent Style Modeling Sequential / Behavioral Style Modeling
Library IEEE;

use IEEE.std_logic_1164.all;

entity nor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end nor2;

architecture dataflow of nor2 is

begin

Y <= A nor B;

end dataflow;

 

Library IEEE;

use IEEE.std_logic_1164.all;

entity nor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end nor2;

architecture behave of nor2 is

begin

process (A,B)

begin

If (A=’0′ and B=’0′) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of a NOR gate

XOR Gate

XOR Gate

Symbol

 

 

 

Function

It produces a high when odd input are high, else produces a LOW output

Modeling Style

Dataflow/Concurrent Modeling : It makes use of the logic equation for modeling. The logic equation of an XOR Gate is :  Y = (X’.Y +X .Y’)

Behavior / Sequential Modeling : This style of modeling makes use of the behavior or the algorithm of the operation. The XOR gate produces a HIGH ‘1’ output when one of its two input is high ‘1’ LOW ‘0’ otherwise.

VHDL Code for Synthesizing XOR Gate

Library IEEE;

use IEEE.std_logic_1164.all;

entity xor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end xor2;

architecture dataflow of xor2 is

begin

Y <= A xor B;

End dataflow;

Library IEEE;

use IEEE.std_logic_1164.all;

entity xor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end xor2;

architecture behav2 of xor2 is

begin

process (A, B)

begin

If (A/=B) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of XOR Gate

NAND Gate

 

NAND Gate

 

 

Function: A NAND gate produces the complement of an AND gate. It produces a high output when any or all inputs are LOW ‘0’ else produces a LOW ‘0’

Modeling Style

Dataflow Style Modeling: It make use of the logic equation for modeling Y= (A.B)’

Behavioral/Sequential Style Modeling:

It makes use of the behavioral or algorithm for the synthesis. i.e. NAND gate produces a HOGH ‘1’ output when any or all inputs are low ‘0’, else it produces a the LOW output

VHDL Code for Synthesizing NAND Gate

Dataflow /Concurrent Style Modeling Behavioral / Sequential Style Modeling
Library IEEE;

use IEEE.std_logic_1164.all;

entity nand2 is

port(

A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC );

end nand2;

architecture behav1 of nand2 is

begin

Y <= A nand B;

 

end behav1;

 

Library IEEE;

use IEEE.std_logic_1164.all;

entity nand2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC );

end nand2;

architecture behav2 of nand2 is

begin

Process (A, B)

Begin

If (A=’1′ and B=’1′) then

Y <= ‘0’;

else

Y <= ‘1’;

end if;

end process;

end behav2;

Simulation of NAND Gate

 

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