VHDL Programs for Half Adder


Write VHDL programs for the following circuits, check the wave forms and the hardware generated for Half Adder

Objective

I. To understand the function and operation of a Half Adder
ii. To learn the modeling styles of Half Adder in VHDL
iii. To synthesize and simulate Half Adder

Theory of a Half Adder:

A half adder is a combinational  circuit that adds two one bit numbers. One of the two bits is the carry from the lower stage or a hardwired HIGH/LOW bit.

 

Symbol and Truth Table

LOGIC Equation

Sum = A’.B + A.B’

Carry = A.B

Modeling Style

Dataflow Modeling of HA

Dataflow/Concurrent Style Modeling : This style makes use of the logic equation of a half adder

Dataflow Modeling of Half Adder

The logic equation of a Half Adder

Sum = A.B’ + A’.B

= A xor B

Carry = A.B

Concurrent VHDL Code to Synthesize a Half Adder

library ieee;                                                — include library
use ieee.std_logic_1164.all;                      — use package
entity halfAdder is                                     — declaration of entity

   port(

A, B : in std_logic;
sum, carry : out std_logic

);
end halfAdder;

architecture dataflow of halfAdder is           — architecture area
begin

sum <= A xor B;
carry <= A and B;

end dataflow;

Simulation of Half Adder

 

Behavioral Modeling of HA

Behavioral Modeling of Half Adder

The logic equation of a Half Adder

Sum = A.B’ + A’.B

= A xor B

Carry = A.B

From the above above logic equations it may be deduced the the output sum is high when A not equal to B. Carry is high when all the inputs are high. We will use this behavior to synthesize the Half Adder.

VHDL Code to Synthesize a Half Adder

library ieee;
use ieee.std_logic_1164.all;
entity halfAdder is

port(

A, B : in std_logic;
sum, carry : out std_logic

);

end halfAdder;
architecture behave of halfAdder is
begin

HA: process

begin

if (A/=B) then

sum<= ‘1’;

carry <= ‘0’;

elsif (A=’1’ and B=’1’) then

sum <= ‘0’;
carry <= ‘1’;

else

sum <= ‘0’;
carry <= ‘0’;

end if;

end process;

end behave;

Simulation of a Half Adder

 

Structural Modeling of HA

Structural Style Modeling of a half Adder

This style of modeling make use of the components instantiation them from the library. The components are the mapped for proper port connection

VHDL Code for synthesizing Half Adder

entity halfAdder is
port (

A, B : in std_logic;
sum, carry : out std_logic

);

endhalfAdder;
architecture struct of halfAdder is

component andGate is                — import AND Gate
port (

A, B : in std_logic;
F : out std_logic

);

end component;
component xorGate is — import XOR Gate
port(

A, B : in std_logic;
F : out std_logic

);

end component;
begin

G1 :xorGate port map(A, B, sum);
G2 :andGate port map(A, B, carry);

endhalfAdder;

Simulation of Half Adder

Summary of Half Adders

  • A half adder is a circuit that produces two outputs a sum and a carry output
  • The logic equation for sum = A’B + AB’
  • The logic equation for carry = A.B
  • Process is a concurrent statement, however all statement inside the process are sequential one.
  • port map statement is used to mapping the input/ Output Ports of Component

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