Design of a Full Adder in VHDL


AIM :Write a VHDL Code to design a Full adder using different modeling style

Objective:

  1. To understand the operation of a Full Adder, logic equation and the truth table
  2. To develop VHDL code for design of VHDL Code in different style of modeling
  3. To synthesize and simulate the Full adder circuit

Theory:

A Full adder is a combinational circuit that adds two one bits numbers along with a
carry from the lower stage and produces  the sum and the carry as output
Block diagram and the truth table

Truth table on the right depicts the generation of sum and carry output when the inputs A, B and C changes.

SoP equations

Sum = A’B’C + A’BC’+ AB’C’ + ABC

= A ⊕ B ⊕ C

Carry   =A’BC + AB’C +ABC’ + ABC

= BC(A’+A) + A(B’C + BC’)

= BC + A(B ⊕ C)

Modeling Style:

Dataflow / Concurrent Style Modeling: This style makes use of the logical equations for synthesizing the circuit. Therefore we’ll use :

sum= A ⊕B ⊕ C

carry = BC + A( B ⊕ C)

Behavioral Style Modeling : This style makes use of the functional behaviour or algorithm to describe the design.

The behaviour can be tested for each and every combination of A, B and C

e.g.

num = A & B & C

if num =”000″ then sum=0; carry =0

and so on

if num= “111” then sum=1 carry=1

Structural Style Modeling: This style makes use of logic gates or other library components for the synthesize of the given circuit. The library and the package must be included at the top of the VHDL code. Then the components are instantiated inside the architecture. Design in structural modeling is shown in figure below:

VHDL Code in different style of modeling

Dataflow Modeling

VHDL Code in Dataflow / Concurrent Style Modeling

 

library ieee;

use ieee.std_logic_1164.all;

entity fullAdder is

port(

A, B C: in std_logic;
sum, Cout : out std_logic

);

end fullAdder;

architecture dataflow of fullAdder is

begin

sum <= A xor B xor C;

carry <= ( (B and C) or (A and ( B xor C)));

End dataflow;

 

RTL Synthesis of FA

Simulation of Full Adder

Behavioral Style

VHDL Code in Behavioral Style

This style makes use of the functional behaviour or algorithm to describe the design.

The behaviour can be tested for each and every combination of A, B and C

e.g.

num = A & B & C     — concatenate signal A,B , C as a string

if num =”000″ then sum=0; carry =0         — test 3-bit string num

and so on

if num= “111” then sum=1 carry=1

VHDL Code to Synthesize Full Adder in Behavioral Modeling

 

libraryieee;

use ieee.std_logic_1164.all;

entityfullAdder is

port(

A, B C: in std_logic;

sum, carry : out std_logic

);

end fullAdder;

architecture behave of fullAdder is

begin

process (A,B,C)

variable num=std_logic_vector(2 downto 0);

begin

num := A & B & C;

if num = “000” then

sum <= ‘0’;  carry <= ‘0’;

elsif num = “001” then

sum <= ‘1’; carry <= ‘0’;

elsif num = “010” then

sum <= ‘1’; carry <= ‘0’;

elsif num = “011” then

sum <= ‘0’; carry <= ‘1’;

elsif num = “100” then

sum <= ‘1’; carry <= ‘0’;

elsif num = “101” then

sum <= ‘0’; carry <= ‘1’;

elsif num = “110” then

sum <= ‘0’; carry <= ‘1’;

elsif num = “111” then

sum <= ‘1’; carry <= ‘1’;

end if;

end process;

End behave;

Simulation of FA

 

 

FA Structural

Structural Modeling of Full Adder

 

A full adder can be constructed using two half adders and an or gate.

 

 

VHDL Code to Synthesize of Full adder using Half Adders

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity FA_str is

Port (

A,B,C : in STD_LOGIC;

sum, carry : out STD_LOGIC

};

end FA_str;

architecture Behavioral of FA_str is

component or_gate is

port (

A, B : in std_logic;

C : out std_logic

);

end component or_gate;

component ha is

port (

A, B : in std_logic;

s, cr: out std_logic

);

end component ha;

signal w1, w2, w3: std_logic;

begin

u1: ha port map (

A => A, B => B, s=> w1, cr=>w2 );

u2: ha port map (

A=> w1, B=> C, s=> sum, cr=> w3 );

u3: or_gate port map (

A=> w2, B=> w3, C=>carry );

end Behavioral;

 

RTL Synthesis of Full Adder

Simulation of Full Adder

 

 

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