Large and Complex circuit are designed using structural Modeling. The designs are usually designed using top-down methodology. The top-down approach is used to decompose the system into modules or subsystems those themselves can be further decomposed into smaller subsystems and this process repeated until no further decomposing is possible.
Each level of decomposition may be designed using any of the four types of modeling in VHDL; dataflow/concurrent style, behavioral/Sequential, Structural Style Modeling. The fourth style is the mixed style of modeling. It is up to the designer which modeling to choose.
The following sections exemplify the synthesis of larger circuits.
For example a 4-bit adder can be decomposed into four 1-bit full adders. We assume here that FA is the smallest component with no further decomposition.
An N-bit adder requires N 1-bit full adders
entity FA is
a, b, c1 : in STD_LOGIC;
s : out STD_LOGIC;
co1 : out STD_LOGIC
architecture dataflo of FA is
s<= a xor b xor c1;
co1<= (a and b) or (c1 and ( a xor b) );
entity adder_Nbit is
generic (N: integer:=8);
a, b : in STD_LOGIC_VECTOR (N-1 downto 0);
ci : in std_logic;
s : out STD_LOGIC_VECTOR (N-1 downto 0);
co : out STD_LOGIC
architecture Behavioral of adder_Nbit is
component FA is
a,b,c1 : in STD_LOGIC;
s, co1 : out STD_LOGIC
signal carry : std_logic_vector(N downto 0);
carry (0) <= ci;
xi: for i in 0 to N-1 GENERATE
Xi: FA PORT MAP
(a=>a(i), b=>b(i), c1=>carry(i), s=>s(i), co1=>carry(i+1));
Behavioral Structural Modeling