VHDL Program for Half Subtractor

AIM:

Write VHDL programs to synthesize a Half subtractor (HS) circuit in VHDL and check the wave forms and the hardware generated
Objective:

  • To learn the VHDL coding for HS
  • To understand the behavior of HS
  • To synthesize and simulate HS

Theory

A half subtractor is a combinational circuit that produces the difference and borrow outputs

The truth table of HS is given below:

A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

The output equations for the sum and carry are given below:
Diff       = AB’ + A’B OR Sum <= A xor B;
Borrow = A’.B

VHDL Coding in different Style of Modeling

Dataflow Modeling of HS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HS is
Port (

A : in STD_LOGIC;

B : in STD_LOGIC;

Diff : out STD_LOGIC;

Borrow : out STD_LOGIC

);

end HS;

architecture dataflow of HS is

begin

Diff <= A xor B;

       Borrow <= (NOT A) and B;

end dataflow;

Behavioural Style of HA

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HS is
Port (

A : in STD_LOGIC;

B : in STD_LOGIC;

Diff : out STD_LOGIC;

Borrow : out STD_LOGIC

);

end HS;

architecture Behavioral of HS is

begin

process(A,B)

begin

if (A =’0′ and B=’0′) THEN

Diff <= ‘0’;

Borrow <= ‘0’;

elsif (A = ‘0’ and B=’1′) THEN

Diff <= ‘1’;

Borrow <= ‘1’;

elsif (A =’1′ and B=’0′) THEN

Diff <= ‘1’;

Borrow <= ‘0’;

elsif (A = ‘1’ and B=’1′) THEN

Diff <= ‘0’;

Borrow <= ‘0’;

else

Diff <= ‘Z’;

Borrow <=’Z’;

end if;

end process;

end Behavioral;

RTL Synthesis of Half Subtractor

Half Subtractor Simulation

Structural Modeling of HA

Structural Style of Modeling

The structural style of modeling of a Half Subtractor make use of XOR, INVERTOR  and AND gate component. See the block diagram of Half Subtractor again (given below) and note the interconnections among various components.

HS_struct

VHDL Code for Half Subtractor

 


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity and_gate is

port (

A,B : in STD_LOGIC;

C: out STD_LOGIC

);

end and_gate;

architecture dataflow of and_gate is

begin

C <= A and B;

end dataflow;
—————————————————————————————-
xor_gate
—————————————————————————————-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity xor_gate is

port (

A,B : in STD_LOGIC;

C: out STD_LOGIC

);

end xor_gate;

architecture dataflow of xor_gate is

begin

C <= A xor B;

end dataflow;
———————————————————————————-
not_gate
———————————————————————————-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity not_gate is

port (

A: in STD_LOGIC;

B: out STD_LOGIC

);

end not_gate;

architecture dataflow of not_gate is

begin

B <= not A;

end dataflow;
——————————————————————————-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity HS_struct is

Port (

X : in STD_LOGIC;

Y : in STD_LOGIC;

Diff : out STD_LOGIC;

Borrow : out STD_LOGIC

);

end HS_struct;

architecture Behavioral of HS_struct is

component xor_gate is

port (

A, B: in STD_LOGIC;

C: out STD_LOGIC

);

end component;

component not_gate is

port (

A : in STD_LOGIC;

B: out STD_LOGIC

);

end component;

component and_gate is

port (

A, B: in STD_LOGIC;

C: out STD_LOGIC

);

end component;

signal Wire : std_logic;

begin

U1 : entity xor_gate port map ( A=>X, B=> Y, C=> Diff );

U2 : entity not_gate port map ( A => X, B => Wire );

U3: entity and_gate port map ( A=> Wire, B=> Y, C=> Borrow );

end Behavioral;

HS_struct

 

Updated: August 3, 2019 — 5:27 pm

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