AIM

Write a VHDL program for a counter and check the wave forms and the hardware generated

Objective:

Objective of this lab is to:

1. Revise the theoretical work
2. Learn the VHDL Coding
3. Synthesize counters using VHDL
4. Verify the functionality using ISIM simulator

Theory:

A digital counter is a sequential circuit consisting of a number of flip-flops connected in some suitable manner to count the sequence of pulses / events applied to it. The counter like a register is a sequential circuit.

Types of Counters

1. Synchronous and Asynchronous counters
2. Single and Multi-Mode Counters (Up counter, Down Counter, Up-Down Counter)
3. Modulus Counter: Modulus-3, Modulus-6, Modulus-10 etc.
4. Shift register counters:- Ring Counter, Johnson Counter etc.
   1. The single and multimode counters are used for single mode that is either up or down counter or multi-mode counter as up/down counter.
   2. The modulus counter on the other hand are the counters that count upto a certain count, a counter that counts 0 through 9 is Modulus-10 counter, Its name come from the number of states that it counts. So we have different modlulus counters as mudulus-3, modulus-6, modulus-10.
   3. Ring counters: these are applications of the shift registers and are of various types such as Ring Counter, Johnson Counter etc.

Applications of Counters: 

1. in counting applications.
2. To measure the time interval between two unknown time instants
3. To measure the frequency of a given signal
4. Counters are useful for digital clocks and timers
5. Used in oven timers, VCR clocks, etc
6. The registers and the counters are found as a very important building block of sequential logic.

Synthesis of Counters using VHDL

Binary Up Counter

Binary up counter in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity binary_counter is

Port (

clk : in  STD_LOGIC;

reset : in  STD_LOGIC;

count : out  STD_LOGIC_VECTOR (3 downto 0)

);

end binary_counter;

architecture Behavioral of binary_counter is

signal  tmp : std_logic_vector(3 downto 0);

begin

process (reset, clk)

begin

if(reset=’1′ )then

tmp<= “0000”;

elsif (clk’event and clk=’1′) then

tmp<= tmp + 1;

end if;

end process;

count<= tmp;

end Behavioral;

Simulation of Binary Up Counter

 

Binary Up-Down Counter

 Binary Up-Down Counter

 library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity up_down_counter is

port (

DIR, CLK: in std_logic;

count_out: out std_logic_vector(7 downto 0)

);

end up_down_counter;

architecture Behavioral of up_down_counter is

signal count   : STD_LOGIC_VECTOR (7 downto 0) := X”00″;

begin

process (CLK)

begin

if (clk’Event and clk = ‘1’) then

if (DIR = ‘1’) then

count<= count + ‘1’;   — counting up

elsif (DIR = ‘0’) then

count<= count – ‘1’;   — counting down

end if;

end if;

end process;

count_out<=   not count;

end Behavioral;

Simulation of Binary Up-Down Counter

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