Interrupt structure of 8085 microprocessor:
8085 IC has six pins from PIN 6 to PIN 11, reserved for interrupts these are TRAM, TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. PIN 11 is the interrupt acknowledgement (INTA’) that is generated by the 8085 processor in response to the different interrupts that arrive at the interrupt pin.
Figure shows the interrupt structure of 8085 microprocessor. Interrupt priority is shown by the decimal numbers on the extreme left of the figure. As can be see that TRAP has the higher priority marked by digit 1 and INTR has the least priority marked by digit 5 on the left of figure.
IVT (Interrupt vector table): IVT contains the interrupt service routine addresses
|Table-1 (IVT interrupt[t vector table)|
The interrupt structure is explained in the following paragraphs:
TRAP is a non-maskable (NMI) and also a vectored interrupt. It is an edge and also level sensitive. TRAP is a highest priority interrupt than any other interrupt, however TRAP has lower priority than HOLD signal issued by the DMA controller.
TRAP once arrives then it cannot be disabled. There are however following two ways to clear the TRAP interrupt.
There TRAP can be overridden by the HOL signal, (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized). TRAP is used for such critical applications such as power failure and emergency shut off.
These interrupts can be masked with two software instructions these are EI (Enable Instruction) and SIM (set Interrupt Mask) instruction.
SIM(set Interrupt Mask) instruction:
This instruction can be used for following purposes:
Bit D7, D6 control the serial I/O function. If D6=1, it will enable serial I/O and D7 bit used to transmit.