OPERATORS

VHDL has a wide set of operators. These are specific to the data types, all operators do not operate on every data types. They are further divided into groups of the same precedence level (priority).Table below shows all operators as per their precedance low to high, row-1 has the lowest priority whereas operators of row-7 has the highest priority. Within each row the priority is from left to right with the leftmost having highest priority.

Class	Operator Precedence Low             high	Same Operator Precedence (Applied Left –to-Right)
1. Logical operators		and	or	nand	nor	xor	xnor
2. Relational operators		=	/=	<	<=	>	>=
3. Shift operators		sll	srl	sla	sra	rol	ror
4.Addition operators		+	=	&
5. Unary operators		+	–
6. Multiplying op.		*	/	mod	rem
7. Miscellaneous op.		**	abs	not

The order of precedence is the highest for the operators of class 7, followed by class 6 with the lowest precedence for class 1. Unless parentheses are used, the operators with the highest precedence are applied first. Operators of the same class have the same precedence and are applied from left to right in an expression. As an example, consider the following std_ulogic_vectors, X (=’010’), Y(=’10’), and Z (‘10101’). The expression

            not X & Y xor Z rol 1 

is equivalent to  ((not X) & Y) xor (Z rol 1)  = ((101) & 10) xor (01011)  =(10110) xor (01011) = 11101. The xor is executed on a bit-per-bit basis.

 The description of the above operators are given below with the help of examples.

miscellaneous operators

** , abs, not

The STD_LOGIC_VECTOR data type can be used in addition and subtraction operations (+ and -) if the STD_LOGIC_SIGNED or the STD_LOGIC_UNSIGNED package of the IEEE library is used. (Otherwise the arithmetic operators can only be used with INTEGER, SIGNED and UNSIGNED data types)

multiplying operators

*, / , mod, rem

The remainder (rem) and modulus (mod) are defined as follows:

              A rem B = A –(A/B)*B                        (in which A/B in an integer)

             A mod B = A – B * N              (in which N is an integer)

The result of the rem operator has the sign of its first operand while the result of the mod operators has the sign of the second operand.

 Some examples of these operators are given below.

  11 rem 4                      results in 3

(-11) rem 4                   results in -3

9 mod 4                        results in 1

7 mod (-4)                    results in –1  (7 – 4*2 = -1).

adding operators

+ , – , &

signal MYBUS                        :std_logic_vector (15 downto 0);

signal STATUS                       :std_logic_vector (2 downto 0);

signal RW, CS1, CS2             :std_logic;

signal MDATA                                  :std_logic_vector ( 0 to 9);

MYBUS <= STATUS & RW & CS1 & SC2 & MDATA;

Other examples are

MYARRAY (15 downto 0) <= “1111_1111” & MDATA (2 to 9);

NEWWORD <= “VHDL” & “93”;

shift operators

Sll, srl, sla, sra, rol, ror

can only be used on BIT_VECTOR data types

variable NUM1          :bit_vector := “10010110”;

            NUM1 srl 2; — will result in the number “00100101”.

When a negative integer is given, the opposite action occurs, i.e. a shift to the left will be a shift to the right. As an example

NUM1 srl –2 would be equivalent to NUM1 sll 2 and give the result “01011000”.

Other examples of shift operations are for the bit_vector A = “101001”

variable A: bit_vector :=”101001”;

A sll 2    –results  in     “100100”

A srl 2    –results in                  “001010”

A sla 2    –results in                  “100111”

A sra 2    –results in                 “111010”

A rol 2    –results in                  “100110”

A ror 2    –results in                 “011010”

relational operators

= (equal) /= (not Equal) < (less than) <= (Less than equal to) > (Less than) >=(Greater than equal to)

BIT and BIT_VECTOR STD_LOGIC and STD_LOGIC_VECTOR (also on STD_ULOGIC, STD_ULOGIC_VECTOR, INTEGER, SIGNED and UNSIGNED)

variable STS               : Boolean;

constant A                  : integer :=24;

            constant B_COUNT   : integer :=32;

            constant C                  : integer :=14;

            STS <= (A < B_COUNT) ;   — will assign the value “TRUE” to STS

            STS <=  ((A >= B_COUNT) or (A > C));     — will result in “TRUE”

            STS <=  (std_logic (‘1’, ‘0’, ‘1’) < std_logic(‘0’, ‘1’,’1’));–makes STS “FALSE”

             type new_std_logic is (‘0’, ‘1’, ‘Z’, ‘-‘);

            variable A1: new_std_logic :=’1’;

            variable A2: new_std_logic :=’Z’;

            STS <=  (A1 < A2); –will result in “TRUE” since ‘1’ occurs to the left of ‘Z’.

logical operators

And, or, nand, nor, xor, xnor

Can operate on- BIT, BIT Vector, STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, STD_ULOGIC_VECTOR,

  Implement the code for the following circuit

ENTITY example1 IS

PORT (x1,x2,x3 : IN BIT;

f : OUT BIT

);

END example1;

ARCHITECTURE LogicFunc OF example1 IS

BEGIN

f <= (x1 AND x2) OR (NOT x2 AND x3);

END LogicFunc;

Question

Define operator in VHDL and explain different types of operators in VHDL.