The sequential constructs refer to the VHDL language constructs that execute in sequence. The different sequential constructs are :

• Wait statement

• If statement

• Case statement

• Loop statement

• Null statement

• Next statement

• Assertion statement

• Report statement

• Procedure call statement

• Return statement

we now discuss all these sequential statements in the  following paragraph :

IF statement:

The IF statement used to transfer the control of the program to another set of sequential statement based on the value of the condition in the expression that evaluates to BOOLEAN value. The syntax of the IF statement is:

Format-1	Format-2	Format-3
IF expression then Statement(s); ELSE Statement(s) END IF	IF expression then Statement(s); ELSIF expression then Statement(s) — END IF	IF expression then IF expression then IF expression then Statement(s); ELSE Statement(s) End if; End if; End if;

The following example illustrates the use of if statement for modeling a 2×1 multiplexer. The inputs to the multiplexer are w0 and w1 and‘s’ is the control input.

LIBRARY ieee;

USE ieee. Std_logic_1164.all;

ENTITY mux_2x1 IS

PORT (w0, w1, s : IN STD_LOGIC;

F : OUT STD_LOGIC);

END mux_2x1;

ARCHITECTURE behave OF mux_2x1 IS

BEGIN

PROCESS (w0,w1,s)

BEGIN

IF s=’0’ THEN

F <= w0;

ELSE

F <= w1;

END IF;

END PROCESS;

END behave;

CASE Statement:

Case statement is used to take the branch of the program to a particular location based on the value of the expression written after the keyword CASE. The examples of different formats of the case statement if given below:

i	ii	iii	iv
CASE expression IS When “op1” => statement; When“op2” => statement; When“op3”=> statement; When others => statement; END CASE;	Case expr IS When op1|op2=> statement; When op3|op4=> statement; When others => statement; END CASE;	case INT_A is when 0 => Z when 1 to 3 => Z when 4|6|8 => Z when others=> Z end case;	Case int_a IS When 0|2|4|6 => z When 1|3|5 => z When others => z End case;

Care should be taken that the choice do not overlap otherwise an VHDL will report an error. Also to note is that range cannot be used with vector type as:

When “000” to “101” this will be error.

The expression in  the CASE statement must take the value as one-dimensional value and must hold discrete values. Different choices may be expressed in single value, range of values, by using ” | “ to mean any one of the ones separated by “ | ”. The choice OTHERS can be used to cover the other left-over range or values of case statement.

Example-1: The mux_2to_1 multiplexer is discussed with CASE statement.

Entity mux_2to_1 IS

PORT (

A, B : in STD_LOGIC;

Sel : in STD_LOGIC;

F : out std_logic

);

End mux_2to_1

Architecture behave_of_mux_cct of mux_2to_1 IS

Constant time_delay: TIME :=10 ns;

Begin

Process ( A,B,Sel)

Variable temp: std_logic;

begin

CASE sel IS

When ‘0’ => temp := A;

When ‘1’ =>temp := B;

when OTHERS =>temp := ‘-‘;

END CASE;

F<= temp after time_delay;

END PROCESS;

END behave_of_mux_cct;

Example-2:

In this example a process defines a data definition named Op_Codes, and a variable Code of type Op_Codes. Now the case statement is used to execute one of the six case which are grouped in two categories.

Library ieee;

Use ieee.std_logic_1164.all;

entity logic_unit is

Port ( a : in STD_LOGIC_vector(3 downto 0);

b : in STD_LOGIC_vector(3 downto 0);

opcode : std_logic_vector(2 downto 0);

y : out STD_LOGIC_vector(3 downto 0)

);

end logic_unit;

architecture Behavioral of logic_unit is

constant and1 : std_logic_vector(2 downto 0):=”011″;

constant or1 : std_logic_vector(2 downto 0):=”100″;

constant xor1 : std_logic_vector(2 downto 0):=”101″;

constant xnor1 : std_logic_vector(2 downto 0):=”110″;

constant nand1 : std_logic_vector(2 downto 0):=”111″;

begin

process(a,b, opcode)

begin

case opcode is

when and1 => Y <= a and b;

when or1 => Y <= a or b;

when xor1 => Y <= a xor b;

when xnor1 => Y <= a xnor b;

when nand1 => Y <= a nand b;

when others => Y <= “0000”;

end case;

end process;

end Behavioral;

NULL STATEMENT

It performs no action and its only function is to pass on to the next statement. It is usually used with the case statement, to indicate that under certain conditions, no action is required. It is also used in process, function and procedures.

The null statement is supported by synthesis tools. Using a null statement in a “combinational process” can result in latches being inferred, unless all signals driven by the process are given unconditional default assignments

case OPCODE is

  when “001” => TmpData := RegA and RegB;
  when “010” => TmpData := RegA or RegB;
  when “100” => TmpData := not RegA;
  when others => null;

end case;

Questions

• Explain If statement with an example.

• Explain Case Statement with an example.

• Short note on NULL statement