Write VHDL programs for synthesizing of DeMultiplexer  Objective: To learn the VHDL coding for Demultiplexer To understand the behavior of Demultiplexer To synthesize and simulate Demultiplexer Theory: A de-multiplexer is a combinational circuit that behavior opposite to a multiplexer. It has a single input, ‘S’ control inputs and 2S as output lines. Only one of the output will be activated by the control / selection lines and the input I will be transferred on the selected output line. Figure below shows the block diagram of the demultiplexer   Output equations: Y0 = I.(S1’.S0’ ) Y1 = I.(S1’.S0) Y2 = I.(S1.S0’ ) Y3 = I.(S1.S0 )   VHDL Code using different styles of Modelling entity DeMux is Port ( I : in  STD_LOGIC; S : in  STD_LOGIC_VECTOR (1 downto 0); Y : out  STD_LOGIC_VECTOR (3 downto 0) ); end

Write VHDL programs for the following circuits, check the wave forms and the hardware generated multiplexer   De-Multiplexer Objective: To learn the VHDL coding for Multiplexer To understand the behavior of Multiplexer To Synthesize multi-bit MUxes To Synthesize larger MUXs using smaller MUXs To simulate Multiplexer Theory: A multiplexer is a combinational circuit which has 2N:1 input output ports with N and control ports. The control port is used to select one of the 2N input and connect it to the output. A multiplexer is also called a switcher as it switches one of several input lines through to a single common output line. The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below: Y = I0 . S’

Parallel Adders Objective: To understand how FA can be cascaded to for adding multi-bit numbers. To develop VHDL code for design of VHDL Code in different style of modeling To synthesize and simulate the parallel adders Theory: A Full adder is a combinational circuit that adds two one bit numbers along with a carry from the lower stage and produces  the sum and the carry as output. This 1-bit FA can be cascaded to perform multi-bit addition. The block diagram shown below gives details of multibit addition.   To perform addition of two n-bit addition: set the carry in bit to '0' connect cout of first stage FA to Cin of next stage FA and so on. Connect Ai, Bi to Fi; wher i is the FA

AIM: To Synthesize the BCD Adder and Generate the hardware and the waveform Objective: To understand basic process of addition To understand the VHDL syntax To Synthesize the BCD adder circuit To simulate verify the result Theory: BCD numbers are represented as 4-bit code. With 4-bits, we can have 16 binary combinations of which only 10 ( 9 through 0) are valid BCD codes. Bit combinations 1010, 1011, 1100, 1101, 1110, 1111 are invalid in BCD representation. While processing the BCD numbers, If the result of adding two BCD numbers fall in this range, the result is required to be adjusted to a correct value. Check the result for a carry out or for result greater than 9. If the result is less than 9, No

Schematic Design Entry in VHDL Open the ISE project navigator by double clicking on the icon Go to file Click new project, Type the name of the project in new project window and click next. Select device family, device, package, speed grade and design flow and click next in the design properties window. Click next and then click finish Click new source ( from Design pane, or project menu-> new source Click Schematic entry , Type file name, add to project, then click next Click finish A new schematic design entry window opens   How to draw schematic: Under the categories in schematic drawing window, there are variety of symbols like counters, decoders, logic etc Select anyone. Click on “Symbol info” in the middle left