AIM : Design of Flip-Flops in VHDL Objective: To revise the basic theory behind the working of the flip flops To understand the syntax of VHDL To synthesize and simulate using VHDL Theory: The theory extend from latches to flip-flops. the basic similarity and differences between a latch and a flip-flop being: Sl Latch Flip-Flop 1 It is a 1-bit memory element It is also a 1-bit memory element 2 It is event based It is clock based 3 Asynchronous operation Synchronous operation 4 Operates n level triggered of enable /clock signal Operates triggering at edges of clock signal 5 VHDL sytax : if clock=’1’ then D <= ‘1’; else D <=’0’; end if; VHDL Syntax: If CLK'EVENT AND CLK='1' THEN If D=’1’ then Q <= ‘1’; Qbar <= ‘0’; Else Q<=’0’; Qbar<=’1’; End if; A flip-flop is used as a one bit storage element in the digital systems. The flip-flops are of various types as

AIM: CODE CONVERTERS IN VHDL Objective: To revise the basic theory behind the working of the Code Converters To synthesize and simulate using VHDL Theory of Code Converters: We, in our day-to-day life deal with numerous forms of data, it can be decimal digits and numbers, alphabets and string or even the special symbol e.g your country currency symbol. We represent this data using code for the computer to process and transmit. As the computer or any other electronic machine does not understand these data patterns, we need to convert them into a form suitable for these machines to understand. The one commonly employed is the binary number system. We also see the real images around us, but when we need to transmit the same at

AIM: Write a VHDL program for a comparator and check the wave forms and the hardware generated Objective: To understand the working of Comparator To learn VHDL codin To understand functional simulation Theory: A comparator is a combinational circuit that compares two objects and returns the outcome as “equal”, “less then”, or “greater then”. The entity comparator is shown below The truth table is given below: INPUTS OUTPUTS a b LT GT EQ 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1   The equations are : EQ = a’.b’ + ab            à a xnor b      i.e. EQ <= ‘1’ when a=b LT = a’b                                               i.e LT <= ‘1’ when (not a and b) GT = ab’                                   i.e GLT <= ‘1’ when (a and (not b)) VHDL Code for Comparator CONCURRENT Code for 1-bit comparator Design in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator is Port ( a : in  STD_LOGIC; b

Priority Encoder A priority Encoder encodes one of the many inputs but only the key having the highest priority is encoded first. If highest priority key is not pressed then the next lower priority key is encoded and so on. The functional table is given below, In the table Y0 and Y1 are the encoded output, output V is an indicator of a valid key press and is high when one of the valid key is pressed:   K0 K1 K2 K3 Y0 Y1 V 0 0 0 0 x x 0 1 0 0 0 0 0 1 x 1 0 0 0 1 1 x x 1 0 1 0 1 x x x 1 1 1 1   The first row in table shows none of the key pressed , so the output (Y0, Y1) are don’t care, and V output is zero indicating none of the valid key pressed. The other rows shows only one input is active and the least numbered keys are