Priority Encoder A priority Encoder encodes one of the many inputs but only the key having the highest priority is encoded first. If highest priority key is not pressed then the next lower priority key is encoded and so on. The functional table is given below, In the table Y0 and Y1 are the encoded output, output V is an indicator of a valid key press and is high when one of the valid key is pressed:   K0 K1 K2 K3 Y0 Y1 V 0 0 0 0 x x 0 1 0 0 0 0 0 1 x 1 0 0 0 1 1 x x 1 0 1 0 1 x x x 1 1 1 1   The first row in table shows none of the key pressed , so the output (Y0, Y1) are don’t care, and V output is zero indicating none of the valid key pressed. The other rows shows only one input is active and the least numbered keys are

Decoder Design using VHDL Objective: To learn how to write VHDL code To Learn how to do functional simulation To do study of the synthesis done by VHDL and the theoretical desin obtained using algebraic solution. Requirement: A computer system installed with XILINX VHDL Theory: Theory: A decoder generally decodes a binary value into a non-binary one by setting exactly one of its ' n'outputs to logic “1”. If a binary decoder receives n inputs (usually grouped as a single binary or Boolean number) it activates one and only one of its 2n outputs based on that input with all other outputs deactivated.   The truth table of a 2x4 decoder is shown below:   S1 S0 O0 O1 O2 O3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1   As seen in the truth table only one of the output line is active depending on

Write VHDL programs for synthesizing of DeMultiplexer  Objective: To learn the VHDL coding for Demultiplexer To understand the behavior of Demultiplexer To synthesize and simulate Demultiplexer Theory: A de-multiplexer is a combinational circuit that behavior opposite to a multiplexer. It has a single input, ‘S’ control inputs and 2S as output lines. Only one of the output will be activated by the control / selection lines and the input I will be transferred on the selected output line. Figure below shows the block diagram of the demultiplexer   Output equations: Y0 = I.(S1’.S0’ ) Y1 = I.(S1’.S0) Y2 = I.(S1.S0’ ) Y3 = I.(S1.S0 )   VHDL Code using different styles of Modelling entity DeMux is Port ( I : in  STD_LOGIC; S : in  STD_LOGIC_VECTOR (1 downto 0); Y : out  STD_LOGIC_VECTOR (3 downto 0) ); end

Write VHDL programs for the following circuits, check the wave forms and the hardware generated multiplexer   De-Multiplexer Objective: To learn the VHDL coding for Multiplexer To understand the behavior of Multiplexer To Synthesize multi-bit MUxes To Synthesize larger MUXs using smaller MUXs To simulate Multiplexer Theory: A multiplexer is a combinational circuit which has 2N:1 input output ports with N and control ports. The control port is used to select one of the 2N input and connect it to the output. A multiplexer is also called a switcher as it switches one of several input lines through to a single common output line. The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below: Y = I0 . S’

Parallel Adders Objective: To understand how FA can be cascaded to for adding multi-bit numbers. To develop VHDL code for design of VHDL Code in different style of modeling To synthesize and simulate the parallel adders Theory: A Full adder is a combinational circuit that adds two one bit numbers along with a carry from the lower stage and produces  the sum and the carry as output. This 1-bit FA can be cascaded to perform multi-bit addition. The block diagram shown below gives details of multibit addition.   To perform addition of two n-bit addition: set the carry in bit to '0' connect cout of first stage FA to Cin of next stage FA and so on. Connect Ai, Bi to Fi; wher i is the FA