BCD Adder VHDL Lab by Ravinder Nath Rajotiya - August 11, 2019August 11, 20190 AIM: To Synthesize the BCD Adder and Generate the hardware and the waveform Objective: To understand basic process of addition To understand the VHDL syntax To Synthesize the BCD adder circuit To simulate verify the result Theory: BCD numbers are represented as 4-bit code. With 4-bits, we can have 16 binary combinations of which only 10 ( 9 through 0) are valid BCD codes. Bit combinations 1010, 1011, 1100, 1101, 1110, 1111 are invalid in BCD representation. While processing the BCD numbers, If the result of adding two BCD numbers fall in this range, the result is required to be adjusted to a correct value. Check the result for a carry out or for result greater than 9. If the result is less than 9, No
Schematic Design Entry in VHDL VHDL Lab by Ravinder Nath Rajotiya - August 11, 2019August 11, 20190 Schematic Design Entry in VHDL Open the ISE project navigator by double clicking on the icon Go to file Click new project, Type the name of the project in new project window and click next. Select device family, device, package, speed grade and design flow and click next in the design properties window. Click next and then click finish Click new source ( from Design pane, or project menu-> new source Click Schematic entry , Type file name, add to project, then click next Click finish A new schematic design entry window opens How to draw schematic: Under the categories in schematic drawing window, there are variety of symbols like counters, decoders, logic etc Select anyone. Click on “Symbol info” in the middle left
VHDL Program for Half Subtractor VHDL Lab by Ravinder Nath Rajotiya - June 10, 2019May 10, 20210 AIM: Write VHDL programs to synthesize a Half subtractor (HS) circuit in VHDL and check the wave forms and the hardware generated Objective: To learn the VHDL coding for HS To understand the behavior of HS To synthesize and simulate HS Theory A half subtractor is a combinational circuit that produces the difference and borrow outputs The truth table of HS is given below: A B Diff Borrow 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 The output equations for the sum and carry are given below: Diff = AB’ + A’B OR Sum <= A xor B; Borrow = A'.B VHDL Coding in different Style of Modeling library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HS is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Diff : out STD_LOGIC; Borrow : out STD_LOGIC ); end HS; architecture dataflow of HS is begin Diff <= A xor B; Borrow <= (NOT A)
Design of Adder Subtractors in VHDL VHDL Lab by Ravinder Nath Rajotiya - April 30, 2019May 10, 20210 AIM : To Synthesize different types of adder subtractor Objectives To understand the working of different types of adder subtractor circuits To develop VHDL code to synthesize different types of adder subtractors To simulate and analyse the different types of adder subtractors Synthesis of Adder Subtractors Large and Complex circuit are designed using structural Modeling. The designs are usually designed using top-down methodology. The top-down approach is used to decompose the system into modules or subsystems those themselves can be further decomposed into smaller subsystems and this process repeated until no further decomposing is possible. Each level of decomposition may be designed using any of the four types of modeling in VHDL; dataflow/concurrent style, behavioral/Sequential, Structural Style Modeling. The fourth style is the mixed style of
Design of a Full Adder in VHDL VHDL Lab by Ravinder Nath Rajotiya - April 29, 2019May 10, 20210 AIM :Write a VHDL Code to design a Full adder using different modeling style Objective: To understand the operation of a Full Adder, logic equation and the truth table To develop VHDL code for design of VHDL Code in different style of modeling To synthesize and simulate the Full adder circuit Theory: A Full adder is a combinational circuit that adds two one bits numbers along with a carry from the lower stage and produces the sum and the carry as output Block diagram and the truth table Truth table on the right depicts the generation of sum and carry output when the inputs A, B and C changes. SoP equations Sum = A'B'C + A'BC'+ AB'C' + ABC = A ⊕ B ⊕ C Carry =A'BC + AB'C +ABC' + ABC =