Design of Adder Subtractors in VHDL VHDL Lab by Ravinder Nath Rajotiya - April 30, 2019May 10, 20210 Share on Facebook Share Send email Mail Print Print Table of Contents Toggle AIM : To Synthesize different types of adder subtractorObjectivesSynthesis of Adder SubtractorsDifferent types of Adder SubtractorsN-bit AdderSynthesis of an 8-bit adder (parallel adder)dataflowSynthesis of N-bit Adder using dataflow ModelingBehavioral StyleStructural StyleSynthesis of N-bit Adder in VHDLSimulation of an 8-bit AdderN-bit Adder/SubtracterBCD AdderRipple Carry Adder AIM : To Synthesize different types of adder subtractor Objectives To understand the working of different types of adder subtractor circuits To develop VHDL code to synthesize different types of adder subtractors To simulate and analyse the different types of adder subtractors Synthesis of Adder Subtractors Large and Complex circuit are designed using structural Modeling. The designs are usually designed using top-down methodology. The top-down approach is used to decompose the system into modules or subsystems those themselves can be further decomposed into smaller subsystems and this process repeated until no further decomposing is possible. Each level of decomposition may be designed using any of the four types of modeling in VHDL; dataflow/concurrent style, behavioral/Sequential, Structural Style Modeling. The fourth style is the mixed style of modeling. It is up to the designer which modeling to choose. The following sections exemplify the synthesis of larger circuits. Different types of Adder Subtractors N-bit Adder Synthesis of an 8-bit adder (parallel adder) Top-down Approach For example a 4-bit adder can be decomposed into four 1-bit full adders. We assume here that FA is the smallest component with no further decomposition. An N-bit adder requires N 1-bit full adders dataflow Synthesis of N-bit Adder using dataflow Modeling Behavioral Style Structural Style Synthesis of N-bit Adder in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA is Port ( a, b, c1 : in STD_LOGIC; s : out STD_LOGIC; co1 : out STD_LOGIC ); end FA; architecture dataflo of FA is begin s<= a xor b xor c1; co1<= (a and b) or (c1 and ( a xor b) ); end dataflo; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adder_Nbit is generic (N: integer:=8); Port ( a, b : in STD_LOGIC_VECTOR (N-1 downto 0); ci : in std_logic; s : out STD_LOGIC_VECTOR (N-1 downto 0); co : out STD_LOGIC ); end adder_Nbit; architecture Behavioral of adder_Nbit is component FA is Port ( a,b,c1 : in STD_LOGIC; s, co1 : out STD_LOGIC ); end component; signal carry : std_logic_vector(N downto 0); begin carry (0) <= ci; xi: for i in 0 to N-1 GENERATE Xi: FA PORT MAP (a=>a(i), b=>b(i), c1=>carry(i), s=>s(i), co1=>carry(i+1)); end GENERATE; co<= carry(N); end Behavioral; Simulation of an 8-bit Adder Behavioral Structural Modeling N-bit Adder/Subtracter BCD Adder Ripple Carry Adder Share on Facebook Share Send email Mail Print Print