Experiment-1 8085 Microprocessor


Experiment-1: To draw and explain-(i)Block diagram and pin diagram of 8085.  ii.  Instruction Set 8085

Objective:

  1. To familiarize with 8085 microprocessor internal blocks and their use
  2. To Learn with the pin diagram of 8085 and their use
  3. To understand the instruction set
  4. to analyze how and where to use the instructions.

Explanation: 

  1. Internal Block diagram of 8085  –  L-3 Internal Architecture of 8085 8085 Microprocessor – Care4you
  2. PIN Diagram of 80858085 PIN and Signal Description 8085 Microprocessor – Care4you

Instruction set of 8085.

The different instructions under data transfer category are listed in table below:

Sl
Data Transfer instructions
Arithmetic instructions
JUMP instructions
Call instructions
Logical instructions
Flag and M/C control  instructions
1
MVI Reg/Mem,8-bit data
ADDReg/Mem
JMP Addr/Lbl
Call Addr
CMP opr
CLC
2
MOV Rd, Rs
ADC Reg/Mem
CALL Addr/Lbl
CC
CPI Immidiate_opr
CMC
3
MOV Rd, M
ADI 8-bit data
RET
CNC
ANA opr
STC
4
LXI Rp,16-bit Data
ACI 8-bit data
RST n
CP
ANI Immediate_opr
CLD
5
LDA 16-bit Address
DAD Rp
JZ Addr/Lbl
CM
XRA opr
STD
6
STA 16-bit Address
SUB Reg/Mem
JNZ Addr/Lbl
CZ
XRI Immediate_opr
CLI
7
LHLD 16-bit Address
SBB Reg / Mem
JC Addr/Lbl
CNZ
ORA opr
STI
8
SHLD 16-bit Address
SUI 8-bit data
JNC Addr/Lbl
CPE
ORI Immediate_opr
WAIT
9
LDAX [Rp]
SBI 8-bit data
JP Addr/Lbl
CPO
CMA opr
HLT
10
STAX [Rp]
INR Reg / Mem
JM Addr/Lbl
CMC
 NOP
11
XCHG
DCR Reg / Mem
JPE Addr/Lbl
STC
ESC
INX Reg pair
JPO Addr/Lbl
LOCK
DCX Reg Pair
DAA

Detailed Instruction Set

8085  Instruction Set

Mnemonic Op SZAPC ~s Description Notes
ACI n CE ***** 7 Add with Carry Immediate A=A+n+CY
ADC A 8F ***** 4 Add with Carry A=A+r+CY(21X)
ADC B 88
ADC C 89
ADC D 8A
ADC E 8B
ADC H 8C
ADC L 8D
ADC M 8E ***** 7 Add with Carry to Memory A=A+[HL]+CY
ADD  A 87 ***** 4 Add A=A+r   (20X)
ADD B 80
ADD C 81
ADD D 82
ADD E 83
ADD H 84
ADD L 85
ADD M 86 ***** 7 Add to Memory A=A+[HL]
ADI n C6 ***** 7 Add Immediate A=A+n
ANAA A7 ****0 4 AND Accumulator A=A&r   (24X)
ANA B A0
ANA C A1
ANA D A2
ANA E A3
ANA H A4
ANA L A5
ANA M A6 ****0 7 AND Accumulator and Memory A=A&[HL]
ANI n E6 **0*0 7 AND Immediate A=A&n
CALL a CD —– 18 Call unconditional -[SP]=PC,PC=a
CC a DC —– 9 Call on Carry If CY=1(18~s)
CM a FC —– 9 Call on Minus If S=1 (18~s)
CMA 2F —– 4 Complement Accumulator A=~A
CMC 3F —-* 4 Complement Carry CY=~CY
CMP r BF ***** 4 Compare A-r     (27X)
CMP M BF ***** 7 Compare with Memory A-[HL]
CNC a D4 —– 9 Call on No Carry If CY=0(18~s)
CNZ a C4 —– 9 Call on No Zero If Z=0 (18~s)
CP a F4 —– 9 Call on Plus If S=0 (18~s)
CPE a EC —– 9 Call on Parity Even If P=1 (18~s)
CPI n FE ***** 7 Compare Immediate A-n
CPO a E4 —– 9 Call on Parity Odd If P=0 (18~s)
CZ a CC —– 9 Call on Zero If Z=1 (18~s)
DAA 27 ***** 4 Decimal Adjust Accumulator A=BCD format
DAD B 9 —-* 10 Double Add BC to HL HL=HL+BC
DAD D 19 —-* 10 Double Add DE to HL HL=HL+DE
DAD H 29 —-* 10 Double Add HL to HL HL=HL+HL
DAD SP 39 —-* 10 Double Add SP to HL HL=HL+SP
DCR r 3D ****- 4 Decrement r=r-1   (0X5)
DCR M 35 ****- 10 Decrement Memory [HL]=[HL]-1
DCX B 0B —– 6 Decrement BC BC=BC-1
DCX D 1B —– 6 Decrement DE DE=DE-1
DCX H 2B —– 6 Decrement HL HL=HL-1
DCX SP 3B —– 6 Decrement Stack Pointer SP=SP-1
DI F3 —– 4 Disable Interrupts
EI FB —– 4 Enable Interrupts
HLT 76 —– 5 Halt
IN p DB —– 10 Input A=[p]
INR r 3C ****- 4 Increment r=r+1   (0X4)
INR M 3C ****- 10 Increment Memory [HL]=[HL]+1
INX B 3 —– 6 Increment BC BC=BC+1
INX D 13 —– 6 Increment DE DE=DE+1
INX H 23 —– 6 Increment HL HL=HL+1
INX SP 33 —– 6 Increment Stack Pointer SP=SP+1
JMP a C3 —– 7 Jump unconditional PC=a
JC a DA —– 7 Jump on Carry If CY=1(10~s)
JM a FA —– 7 Jump on Minus If S=1 (10~s)
JNC a D2 —– 7 Jump on No Carry If CY=0(10~s)
JNZ a C2 —– 7 Jump on No Zero If Z=0 (10~s)
JP a F2 —– 7 Jump on Plus If S=0 (10~s)
JPE a EA —– 7 Jump on Parity Even If P=1 (10~s)
JPO a E2 —– 7 Jump on Parity Odd If P=0 (10~s)
JZ a CA —– 7 Jump on Zero If Z=1 (10~s)
LDA a 3A —– 13 Load Accumulator direct A=[a]
LDAX B 0A —– 7 Load Accumulator indirect A=[BC]
LDAX D 1A —– 7 Load Accumulator indirect A=[DE]
LHLD addr 2A —– 16 Load HL Direct HL=[a]
LXI B,nn 1 —– 10 Load Immediate BC BC=nn
LXI D,nn 11 —– 10 Load Immediate DE DE=nn
LXI H,nn 21 —– 10 Load Immediate HL HL=nn
LXI SP,nn 31 —– 10 Load Immediate Stack Ptr SP=nn
MOV A,A 7F A=A
MOV A,B 78 —– 4 Move register to register A=B   (1XX)
MOV A,C 79 A = C
MOV A,D 7A
MOV A,E 7B
MOV A,H 7C
MOV A,L 7D
MOV A,M 7E A=[HL]
MOV B,A 47
MOV B,B 40
MOV B,C 41
MOV B,D 42
MOV B,E 43
MOV B,H 44
MOV B,L 45 B=L
MOV B,M 46 B=[HL]
MOV C,A 4F
MOV C,B 48
MOV C,C 49
MOV C,D 4A
MOV C,E 4B
MOV C,H 4C
MOV C,L 4D C=L
MOV C,M 4E C==[HL]
MOV D,A 57
MOV D,B 50
MOV D,C 51
MOV D,D 52
MOV D,E 53
MOV D,H 54
MOV D,L 55 D=L
MOV D,M 56 D=[HL]
MOV E,A 5F
MOV E,B 58
MOV E,C 59
MOV E,D 5A
MOV E,E 5B
MOV E,H 5C
MOV E,L 5D
MOV E,M 5E E=[HL]
MOV H,A 67
MOV H,B 60
MOV H,C 61
MOV H,D 62
MOV H,E 63
MOV H,H 64
MOV H,L 65
MOV H,M 66 H=[HL]
MOV L,A 6F
MOV L,B 68
MOV L,C 69
MOV L,D 6A
MOV L,E 6B
MOV L,H 6C
MOV L, L 6D
MOV L, M 6E
MOV M,A 77 —– 7 Move register to Memory [HL]=A (16X)
MOV M,B 70 [HL]=B
MOV M,C 71 [HL]=C
MOV M,D 72
MOV M,E 73
MOV M,H 74
MOV M,L 75
MOV L,M 6E —– 7 Move Memory to register r=[HL]  (1X6)
MVI r,n 3E —– 7 Move Immediate r=n     (0X6)
MVI M,n 36 —– 10 Move Immediate to Memory [HL]=n
NOP 0 —– 4 No Operation
ORA r B7 **0*0 4 Inclusive OR Accumulator A=Avr   (26X)
ORA M B6 **0*0 7 Inclusive OR Accumulator A=Av[HL]
ORI n F6 **0*0 7 Inclusive OR Immediate A=Avn
OUT p D3 —– 10 Output [p]=A
PCHL E9 —– 6 Jump HL indirect PC=[HL]
POP B C1 —– 10 Pop BC BC=[SP]+
POP D D1 —– 10 Pop DE DE=[SP]+
POP H E1 —– 10 Pop HL HL=[SP]+
POP PSW F1 —– 10 Pop Processor Status Word {PSW,A}=[SP]+
PUSH B C5 —– 12 Push BC -[SP]=BC
PUSH D D5 —– 12 Push DE -[SP]=DE
PUSH H E5 —– 12 Push HL -[SP]=HL
PUSH PSW F5 —– 12 Push Processor Status Word -[SP]={PSW,A}
RAL 17 —-* 4 Rotate Accumulator Left A={CY,A}<-
RAR 1F —-* 4 Rotate Accumulator Righ A=->{CY,A}
RET C9 —– 10 Return PC=[SP]+
RC D8 —– 6 Return on Carry If CY=1(12~s)
RIM 20 —– 4 Read Interrupt Mask A=mask
RM F8 —– 6 Return on Minus If S=1 (12~s)
RNC D0 —– 6 Return on No Carry If CY=0(12~s)
RNZ C0 —– 6 Return on No Zero If Z=0 (12~s)
RP F0 —– 6 Return on Plus If S=0 (12~s)
RPE E8 —– 6 Return on Parity Even If P=1 (12~s)
RPO E0 —– 6 Return on Parity Odd If P=0 (12~s)
RZ C8 —– 6 Return on Zero If Z=1 (12~s)
RLC 7 —-* 4 Rotate Left Circular A=A<-
RRC 0F —-* 4 Rotate Right Circular A=->A
RST z C7 —– 12 Restart              (3X7) -[SP]=PC,PC=z
SBB A 9F ***** 4 Subtract with Borrow A=A-r-CY
SBB B 98
SBB C 99
SBB D 9A
SBB E 9B
SBB H 9C
SBB L 9D
SBB M 9E ***** 7 Subtract with Borrow A=A-[HL]-CY
SBI n DE ***** 7 Subtract with Borrow Immed A=A-n-CY
SHLD a 22 —– 16 Store HL Direct [a]=HL
SIM 30 —– 4 Set Interrupt Mask mask=A
SPHL F9 —– 6 Move HL to SP SP=HL
STA a 32 —– 13 Store Accumulator [a]=A
STAX B 2 —– 7 Store Accumulator indirect [BC]=A
STAX D 12 —– 7 Store Accumulator indirect [DE]=A
STC 37 1 4 Set Carry CY=1
SUB A 97 ***** 4 Subtract A=A-r   (22X)
SUB B 90
SUB C 91
SUB D 92
SUB E 93
SUB H 94
SUB L 95
SUB M 96 ***** 7 Subtract Memory A=A-[HL]
SUI n D6 ***** 7 Subtract Immediate A=A-n
XCHG EB —– 4 Exchange HL with DE HL<->DE
XRA A AF **0*0 4 Exclusive OR Accumulator A=A xr A (clears A)   (25X)
XRA B A8
XRA C A9
XRA D AA
XRA E AB
XRA H AC
XRA L AD
XRA M AE **0*0 7 Exclusive OR Accumulator A=Ax[HL]
XRI n EE **0*0 7 Exclusive OR Immediate A=Axn
XTHL E3 —– 16 Exchange stack Top with HL [SP]<->HL

VIVA QUESTIONS

Que-1: Explain the various internal blocks of 8085 microprocessor

Ans:

  • Register File
  • Address Buffers
  • Instruction Decoder
  • Timing and control Unit
  • ALU
  • Interrupt System
  • Serial I/O

Que-2: What are different classification of 8085 instructions

Ans:

  • Data Transfer Instructions
  • Arithmetic Instructions
  • Logical Instructions
  • Shift and Rotate Instructions
  • Branch type instructions
  • Machine control instructions

Que-3: Name the arithmetic Instructions

Ans:

  • ADD
  • ADC
  • ADI
  • SUB
  • SBB
  • SBI
  • INX
  • INR
  • DCR

Que-4: Name some direct addressing Instructions

Ans:

  • LHLD
  • SHLD
  • LDA
  • STA

 

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