Branch Type Instructions 8086

by Ravinder Nath Rajotiya - 0

Branch Instruction: The branch instruction is used to transfer the control of the program to a new address. This branch can be Conditional or Unconditional. Once the branch is taken the execution of instructions will take place from this new address called branch address. Usually the Conditional branch is taken after the ADD, SUB, INC, DEC  and the instructions used to implement the LOOP.  When these types of instructions are executed, the CS and IP registers get loaded with new values of CS and IP corresponding to the location where a branch is required. The branch instruction can be one of the following types. Unconditional Jump instructions: JMP, CALL, RET, INT N, INTO, IRET, LOOP, Conditional Jump instructions: JA/JNBE, JAE/JNB, JB/JNAE, JC, JNC, JE /JZ, JNE

Logical and Shift and Rotate Instructions 8086

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LOGICAL Group of Instructions. Bit manipulation instruction Bit Manipulation instructions : The instruction in this category operate on bits. The instruction can set, reset or even can test a particular bit. These instructions include : Logical instructions: NOT, AND, OR, XOR and Test. FORMAT Example Comments Flags Affected NOT Source (R/M) MOV BL, 35h NOT BL BL=00110101 BL= 11001010 AND (R/M), Imm./ R/M MOV AL, 35h AND AL, 0Fh AL=00110101 AL=AL.0Fh= 00000101 CF=OF=0, AF=? PF, SF, ZF updated OR (R/M), Imm./ R/M MOV BL, 22h MOV CL, FFh OR BL, CL BL=00010110 CL=11111111 BL=BL+CL=11111111 CF=OF=0, AF=? PF, SF, ZF updated XOR (R/M), Imm./ R/M MOV AL, 55h XOR AL, FAh AL=01010101 AL xor FAh=10100111 CF=OF=0, AF=? PF, SF, ZF updated TEST R?M, Imme/R/M MOV AL, 51h TEST AL, 80h AL=01010001 Test AL,80 test if the MSB is 0 or not; if msb is zer0 Z flag will be set. CF=OF=0, AF=? PF, SF, ZF updated   2.  Shift and Rotate operation These instructions are

Timer Programming in 8051

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Programming 8051 Timers Registers used for normal operation (No interrupts) TMOD, TH1,TL1, TH0, TL0, and TCON TMOD to set the Mode Timer Register to set the count TCON to start and stop the timer Registers used for Interrupt operation IE, TMOD, TH1,TL1, TH0, TL0, and TCON TMOD to set the Mode Timer-0 and Timer-1 Register to set the count TCON to start and stop the timer Register Formats: Interrupt Enable (IE) Register IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 EA ET2 ES ET1 EX1 ET0 EX0 =0, disable =1 enable -- Enable/disable serial port interrupt Enable/disable timer-1 Ov interrupt Enable/disable external interrupt-1 Enable/disable timer-0 Ov interrupt Enable/disable external interrupt-0   TMOD Register: Timer-1 Timer-0 GATE C/T’ M1 M0 GATE C/T’ M1 M0 =1; The timer/counter enabled while INTx and TRx bit is set =0, timer enabled whenever TRx bit is set 1 = Counter 0=Timer 00=13 bit timer mode (8-bit timer/counter with TLx as 5-bit prescalar 01=16 bit timer mode, THx and TLx cascaded,

Arithmetic Instruction (8086)

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Arithmetic Instructions The instruction in this group include ADD, ADC, INC, AAA, DAA, SUB, SBB, DEC, NEG, CMP, AAS, DAS,  MUL, IMUL, AAM, DIV, IDIV, AAD, CBW, BWD. These instruction require two operands which act as destination and the source. Almost all the instructions affect the flags. Instruction Format Flags affected Description Processing ADD ADD Dst, Src AF, CF, OF, PF, SF,ZF Add Dst and Src with result in Dst Dst = Dst+Src ADC ADC Dst, Src AF, CF, OF, PF, SF,ZF Add Dst and Src and the carry with result in Dst Dst = Dst+Src + Cy AAA AAA Affects AF and CF all others PF, ZF, SF, OF are unaffected This instruction follows the addition of unpacked BCD operands. Adjust ASCII addition result, result in AX. The result in AL is changed to unpacked BCD, AL(7-4) cleared, CF is

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