Design of Register using VHDL VHDL Lab by Ravinder Nath Rajotiya - August 12, 2019August 12, 20190 AIM Write VHDL programs for the following circuits, check the wave forms and the hardware generated register shift register Objective: The objective of this lab is to : revise the theory behind the working of the registers To learn VHDL coding for the registers Synthesize register using VHDL Verify the operation using functional Simulation using ISIM Theory: Registers are built using combination of flip-flops. They are the internal storage units for any digital systems. They are of different sizes and are used for temporary storage of memory address(MAR), data to be written to main memory(write buffers), data to be read from memory (read buffers), status condition of an ALU (Flag/ status register). Different types of Registers Serial-in-serial-out shift register Serial-in-parallel-out shift register Parallel-in-Serial-out shift
Design of Counters using VHDL VHDL Lab by Ravinder Nath Rajotiya - August 12, 2019May 10, 20210 AIM Write a VHDL program for a counter and check the wave forms and the hardware generated Objective: Objective of this lab is to: Revise the theoretical work Learn the VHDL Coding Synthesize counters using VHDL Verify the functionality using ISIM simulator Theory: A digital counter is a sequential circuit consisting of a number of flip-flops connected in some suitable manner to count the sequence of pulses / events applied to it. The counter like a register is a sequential circuit. Types of Counters Synchronous and Asynchronous counters Single and Multi-Mode Counters (Up counter, Down Counter, Up-Down Counter) Modulus Counter: Modulus-3, Modulus-6, Modulus-10 etc. Shift register counters:- Ring Counter, Johnson Counter etc. The single and multimode counters are used for single mode that is either up
Design of Flip-Flops in VHDL VHDL Lab by Ravinder Nath Rajotiya - August 12, 2019August 12, 20190 AIM : Design of Flip-Flops in VHDL Objective: To revise the basic theory behind the working of the flip flops To understand the syntax of VHDL To synthesize and simulate using VHDL Theory: The theory extend from latches to flip-flops. the basic similarity and differences between a latch and a flip-flop being: Sl Latch Flip-Flop 1 It is a 1-bit memory element It is also a 1-bit memory element 2 It is event based It is clock based 3 Asynchronous operation Synchronous operation 4 Operates n level triggered of enable /clock signal Operates triggering at edges of clock signal 5 VHDL sytax : if clock=’1’ then D <= ‘1’; else D <=’0’; end if; VHDL Syntax: If CLK'EVENT AND CLK='1' THEN If D=’1’ then Q <= ‘1’; Qbar <= ‘0’; Else Q<=’0’; Qbar<=’1’; End if; A flip-flop is used as a one bit storage element in the digital systems. The flip-flops are of various types as
Design of Code Converters in VHDL VHDL Lab by Ravinder Nath Rajotiya - August 11, 2019August 12, 20190 AIM: CODE CONVERTERS IN VHDL Objective: To revise the basic theory behind the working of the Code Converters To synthesize and simulate using VHDL Theory of Code Converters: We, in our day-to-day life deal with numerous forms of data, it can be decimal digits and numbers, alphabets and string or even the special symbol e.g your country currency symbol. We represent this data using code for the computer to process and transmit. As the computer or any other electronic machine does not understand these data patterns, we need to convert them into a form suitable for these machines to understand. The one commonly employed is the binary number system. We also see the real images around us, but when we need to transmit the same at
Design of Comparator in VHDL VHDL Lab by Ravinder Nath Rajotiya - August 11, 2019August 11, 20190 AIM: Write a VHDL program for a comparator and check the wave forms and the hardware generated Objective: To understand the working of Comparator To learn VHDL codin To understand functional simulation Theory: A comparator is a combinational circuit that compares two objects and returns the outcome as “equal”, “less then”, or “greater then”. The entity comparator is shown below The truth table is given below: INPUTS OUTPUTS a b LT GT EQ 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 The equations are : EQ = a’.b’ + ab à a xnor b i.e. EQ <= ‘1’ when a=b LT = a’b i.e LT <= ‘1’ when (not a and b) GT = ab’ i.e GLT <= ‘1’ when (a and (not b)) VHDL Code for Comparator CONCURRENT Code for 1-bit comparator Design in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator is Port ( a : in STD_LOGIC; b